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| TMP92FD54AI CMOS 32-bit Micro-controller TMP92FD54AIF 1. Outline and Device Characteristics TMP92FD54AI is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92FD54AI is a micro-controller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92FD54AI is housed in a 100-pin mini flat package. Device characteristics are as follows: (1) CPU : 32-bit CPU(900/H1 CPU) Compatible with TLCS-900,900/L,900/L1,900/H,900/H2's instruction code 16Mbytes of linear address space General-purpose register and register banks Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case) Minimum instruction execution time : 50ns(at 20MHz) Internal data bus : 32-bit Internal memory Internal RAM : 32K-byte Internal ROM : 512K-byte Flash E2PROM 3K-byte Mask ROM (for Flash boot mode) (2) 92FD54AI-1 2006-01-27 TMP92FD54AI (3) External memory expansion 16M-byte linear address space (memory mapped I/O) External data bus : 8bit(for external I/O expansion) * Can't use upper address bus when built-in I/Os are selected Memory controller (MEMC) Chip select output : 1 channel (5) 8-bit timer : 8 channels 8-bit interval timer mode (8 channels) 16-bit interval timer mode (4 channels) 8-bit programmable pulse generation (PPG) output mode (4 channels) 8-bit pulse width modulation (PWM) output mode (4 channels) 16-bit timer : 2 channels 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) output mode Frequency measurement mode Pulse width measurement mode Time differential measurement mode Serial interface (SIO) : 2 channels I/O interface mode Universal asynchronous receiver transmitter (UART) mode Serial expansion interface (SEI) : 1 channel Baud rate 4/2/0.5Mbps at fc=20MHz. Serial bus interface (SBI) : 3 channels Clocked-synchronous 8-bit serial interface mode I2C bus mode (10) CAN controller : 1channel Supports CAN version 2.0B. 16 mailboxes (11) 10-bit A/D converter (ADC) : 12 channels A/D conversion time 8sec @fc=20MHz. Total tolerance +/- 3LSB (excluding quantization error) Scan mode for all 12channels (12) Watch dog timer (WDT) (13) Timer for real-time clock (RTC) Can operate with only low frequency oscillator. (14) Interrupt controller (INTC) : 60 interrupt sources 9 interrupts from CPU 42 internal interrupt vectors 9 external interrupt vectors (15) I/O Port : 68pins (16) Standby mode Four modes : IDLE3,IDLE2,IDLE1 and STOP STOP mode can be released by 9 external inputs. (17) Internal voltage detection flag (RAMSTB) (9) (4) (6) (7) (8) 92FD54AI-2 2006-01-27 TMP92FD54AI (18) Power supply voltage VCC5 = 4.5V to 5.25V VCC3 = 3.3V (VCC3 Connect to REGOUT; built-in voltage regulator.) (19) (20) Operating temperature : -40 to 85 degree C Package : P-LQFP100-1414-0.50C 92FD54AI-3 2006-01-27 TMP92FD54AI PG0toPG7 (AN0toAN7) PL0toPL3 (AN8toAN11) ADVCC ADVSS VREFH VREFL (TXD0)PF0 (RXD0)PF1 (SCLK0/ CTS0 )PF2 (TXD1)PF3 (RXD1)PF4 (SCLK1/ CTS1 )PF5 (TX)PF6 (RX)PF7 (TI0/INT1)PC0 (TO1)PC1 10-BIT 12CH A/D CONVERTER XWA XBC XDE SERIAL I/O Channel 0 SERIAL I/O Channel 1 CAN CONTROLLER W B D H IX IY IZ SP 32 bits SR P C A C E L Regulator REGEN REGOUT X1 X2 CLK XT1 XT2 RESET XHL XIX XIY XIZ XSP OSC RTC F INTERRUPT CONTROLLER AM0 AM1 TEST0 TEST1 NMI INT0 P00toP07 (D0toD7) P40toP47 (A0toA7) P70( RD ) P71( WR ) P73( CS ) P74 P75( WAIT ) PN0(SCK0) PN1(SO0/SDA0) PN2(SI0/SCL0) PN3(SCK1/A12) PN4(SO1/SDA1/A13) PN5(SI1/SCL1/A14) PM4(SCK2) PN6(SO2/SDA2/A15) P72(SI2/SCL2) 8BIT TIMER (TIMER0) 8BIT TIMER (TIMER1) 8BIT TIMER (TIMER2) WATCH-DOG TIMER REAL TIME CLOCK (RTC) PORT0 PORT4 32KB RAM PORT7 (TO3/INT2)PC2 (TI4/INT3)PC3 8BIT TIMER (TIMER3) 8BIT TIMER (TIMER4) 8BIT TIMER (TIMER5) 8BIT TIMER (TIMER6) 8BIT TIMER (TIMER7) 16BIT TIMER (TIMER8) 16BIT TIMER (TIMERA) 3K-byte Mask ROM (for Flash boot mode) SERIAL EXP.I/F 512KB Flash E2PROM SERIAL BUS I/F Channel 0 SERIAL BUS I/F Channel 1 SERIAL BUS I/F Channel 2 (TO5)PC4 (TO7/INT4)PC5 (TI8/WUINT0/INT5/A16)PD0 (TI9/WUINT1/INT6/A17)PD1 (TO8/WUINT2/A18)PD2 (TO9/WUINT3/A19)PD3 (TIA/WUINT4/INT7/A20)PD4 (TIB/WUINT5/A21)PD5 (TOA/WUINT6/A22)PD6 (TOB/WUINT7/A23)PD7 PM0( SS /A8) PM1(MOSI/A9) PM2(MISO/A10) PM3(SECLK/A11) Figure 1 TMP92FD54AI block diagram 92FD54AI-4 2006-01-27 CONNECT 900/H1 CPU DVSS[6] DVCC5[5] DVCC3[3] TMP92FD54AI 2. Pin Assignment and Functions 2.1 Pin Assignment 095 090 085 080 ADVSS ADVCC VREFL VREFH RX/PF7 TX/PF6 CTS1/SCLK1/PF5 RXD1/PF4 TXD1/PF3 CTS0/SCLK0/PF2 RXD0/PF1 TXD0/PF0 DVSS PM4/SCK2 DVCC5 A8/SS/PM0 A9/MOSI/PM1 A10/MISO/PM2 A11/SECLK/PM3 D0/P00 D1/P01 D2/P02 D3/P03 D4/P04 D5/P05 01 076 100 PL3/AN11 PL2/AN10 PL1/AN9 PL0/AN8 PG7/AN7 PG6/AN6 PG5/AN5 PG4/AN4 PG3/AN3 PG2/AN2 PG1/AN1 PG0/AN0 DVSS P75/WAIT DVCC3 P74 P73/CS P72/SI2/SCL2 P71/WR P70/RD AM0 RESET AM1 CLK TEST0 75 05 70 10 TMP92FD54AIF (P-LQFP100-1414-0.50C) 65 14 x 14 x 1.4 15 TOP VIEW 60 20 55 26 30 35 40 45 D6/P06 D7/P07 A0/P40 A1/P41 A2/P42 A3/P43 A4/P44 A5/P45 A6/P46 A7/P47 DVCC3 INT0 DVSS NMI DVCC5 A16/WUINT0/INT5/TI8/PD0 A17/WUINT1/INT6/TI9/PD1 A18/WUINT2/TO8/PD2 A19/WUINT3/TO9/PD3 A20/WUINT4/INT7/TIA/PD4 A21/WUINT5/TIB/PD5 A22/WUINT6/TOA/PD6 A23/WUINT7/TOB/PD7 REGOUT DVCC5 92FD54AI-5 50 25 51 DVCC5 X1 DVSS X2 TEST1 XT1 XT2 DVCC3 PN6/SO2/SDA2/A15 PN5/SI1/SCL1/A14 PN4/SO1/SDA1/A13 PN3/SCK1/A12 DVSS PN2/SI0/SCL0 DVCC5 PN1/SO0/SDA0 PN0/SCK0 PC0/TI0/INT1 PC1/TO1 PC2/TO3/INT2 PC3/TI4/INT3 PC4/TO5 PC5/TO7/INT4 REGEN DVSS 2006-01-27 TMP92FD54AI 2.2 Pin names and functions The following table shows the names and functions of the input/output pins. Pin Number of In/Out Function number pins P00..P07 (CMOS) in/out Port 0: I/O port. Input or output specifiable in units of bits. 20th...27th 8 D0..D7 (TTL) in/out Data: Data bus 0 to 7. in/out Port4: I/O port. Input or output specifiable in units of bits. P40..P47 8 28th...35th out Address: Address bus 0 to 7. A0..A7 in/out Port70: I/O port. P70 81st 1 out Read: Outputs strobe signal to read external memory. RD Pin name P71 WR P72 SI2 SCL2 P73 CS P74 P75 WAIT PC0 TI0 INT1 PC1 TO1 PC2 TO3 INT2 PC3 TI4 INT3 PC4 TO5 PC5 TO7 INT4 PD0 TI8 INT5 A16 WUINT0 PD1 TI9 INT6 A17 WUINT1 PD2 TO8 A18 WUINT2 PD3 TO9 A19 WUINT3 82nd 83rd 84th 85th 87th 58th 57th 56th 55th 54th 53rd 1 1 1 1 1 1 1 1 1 1 1 in/out Port 71: I/O port. out Write: Output strobe signal to write external memory. Port 72: I/O port. in/out SBI channel 2: Input data at SIO mode SBI channel 2: Clock input/output at IC mode in/out Port 73: I/O port. out Chip select: Outputs "low" if address is within specified address area. in/out Port 74: I/O port. in/out Port 75: I/O port. in Wait: Signal used to request CPU bus wait. Port C0: I/O port. Timer input 0: Input pin for timer 0. INT1 Interrupt request pin 1: Rising-edge interrupt request pin. Port C1: I/O port. Timer output 1: Output pin for timer 1. Port C2: I/O port. Timer output 3: Output pin for timer 3. INT2 Interrupt request pin 2: Rising-edge interrupt request pin. Port C3: I/O port. INT3 Timer input 4: Input pin for timer 4. Interrupt request pin 3: Rising-edge interrupt request pin. Port C4: I/O port. Timer output 5: Output pin for timer 5. Port C5: I/O port. INT4 Timer output 7: Output pin for timer 7. Interrupt request pin 4: Rising-edge interrupt request pin. Port D0: I/O port. INT5 Timer input 8: Input pin for timer 8. Interrupt request pin 5: Interrupt request pin with programmable rising/falling WUINT0 edge. out Address: Address bus 16. Wake up input 0: Wake up request pin with programmable rising, falling or both in falling and rising edge. in/out Port D1: I/O port. WUINT1 INT6 in Timer input 9: Input pin for timer 9. in Interrupt request pin 6: Rising-edge interrupt request pin. out Address: Address bus 17. in Wake up input 1: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port D2: I/O port. out Timer output 8: Output pin for timer 8 WUINT2 out Address: Address bus 18. in Wake up input 2: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port D3: I/O port. out Timer output 9: Output pin for timer 9 WUINT3 out Address: Address bus 19. in Wake up input 3: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out in in in/out out in/out out in in/out in in in/out out in/out out in in/out in in 41st 1 42nd 1 43rd 1 44th 1 92FD54AI-6 2006-01-27 TMP92FD54AI Pin name PD4 TIA INT7 A20 WUINT4 PD5 TIB A21 WUINT5 PD6 TOA A22 WUINT6 PD7 TOB A23 WUINT7 PF0 TXD0 PF1 RXD0 PF2 SCLK0 CTS0 PF3 TXD1 PF4 RXD1 PF5 SCLK1 Pin number Number of pins In/Out Function 45th 1 46th 1 47th 1 48th 1 12th 11th 10th 9th 8th 7th 1 1 1 1 1 1 1 1 8 4 in/out Port D4: I/O port. INT7 Timer input A: Input pin for timer A in Interrupt request pin 7: Interrupt request pin with programmable rising/falling in edge. WUINT4 out Address: Address bus 20. Wake up input 4: Wake up request pin with programmable rising, falling or both in falling and rising edge. in/out Port D5: I/O port. WUINT5 Timer input B: Input pin for timer B. in out Address: Address bus 21. Wake up input 5: Wake up request pin with programmable rising, falling or both in falling and rising edge. in/out Port D6: I/O port. WUINT6 out Timer output A: Output pin for timer A. out Address: Address bus 22. in Wake up input 6: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port D7: I/O port. WUINT7 out Timer output B: Output pin for timer B. out Address: Address bus 23. in Wake up input 7: Wake up request pin with programmable rising, falling or both falling and rising edge. in/out Port F0: I/O port. out Serial interface channel 0: Transmission data. in/out Port F1: I/O port. in Serial interface channel 0: Receive data. in/out Port F2: I/O port. in/out Serial interface channel 0: Clock input/output. in Serial interface channel 0: Data ready to send. (Clear-to-send) in/out out in/out in in/out in/out in in/out out in/out in in in in in Port F3: I/O port. Serial interface channel 1: Transmission data. Port F4: I/O port. Serial interface channel 1: Receive data. Port F5: I/O port. Serial interface channel 1: Clock input/output. Serial interface channel 1: Data ready to send. (Clear-to-send) Port F6: I/O port. CAN: Transmission data. Port F7: I/O port. CAN: Receive data. Port G: Input-only port. Analog input 0 to 7: AD converter input pins. Port L0 to L3: Input-only port. Analog input 8 to 11: AD converter input pins. CTS1 PF6 6th TX PF7 5th RX PG0..PG7 89th...96th AN0..AN7 PL0..PL3 AN8..AN1 97th...100th 1 PM0 16th SS A8 PM1 MOSI 17th A9 PM2 MISO 18th A10 PM3 SECLK 19th A11 PM4 14th SCK2 PN0 59th SCK0 1 in/out Port M0: I/O port. in SEI: Slave select input. out Address: Address bus 8. in/out in/out out in/out in/out out in/out in/out out in/out in/out in/out in/out Port M1: I/O port. SEI: Master output, slave input. Address: Address bus 9. Port M2: I/O port. SEI: Master input, slave output. Address: Address bus 10. Port M3: I/O port. SEI: Clock input/output. Address: Address bus 11. Port M4: I/O port. SBI channel 2: Clock input/output at SIO mode. Port N0: I/O port. SBI channel 0: Clock input/output at SIO mode. 1 1 1 1 1 92FD54AI-7 2006-01-27 TMP92FD54AI Pin name PN1 SO0 SDA0 PN2 SI0 SCL0 PN3 SCK1 A12 PN4 SO1 SDA1 A13 PN5 SI1 SCL1 A14 PN6 SO2 SDA2 A15 NMI INT0 AM0,1 TEST0,1 CLK X1/X2 XT1/XT2 RESET VREFH VREFL ADVCC ADVSS DVCC5 DVCC3 DVSS REGOUT REGEN Pin number 60th 62nd 64th Number of pins 1 1 1 In/Out in/out out in/out in/out in in/out in/out in/out out in/out out in/out out in/out in in/out out Function 65th 1 66th 1 67th 1 39th 1 Port N1: I/O port. SBI channel 0: Output data input/output at SIO mode SBI channel 0: Data input/output at IC mode Port N2: I/O port. SBI channel 0: Input data at SIO mode SBI channel 0: Clock input/output at IC mode Port N3: I/O port. SBI channel 1: Clock input/output at SIO mode Address: Address bus 12. Port N4: I/O port. SBI channel 1: Output data at SIO mode SBI channel 1: Data input/output at IC mode Address: Address bus 13. Port N5: I/O port. SBI channel 1: Input data at SIO mode SBI channel 1: Clock input/output at IC mode Address: Address bus 14 Port N6: I/O port. in/out SBI channel 2: Output data at SIO mode out SBI channel 2: data input output at I2C mode Address: Address bus 15. Non-maskable interrupt: Interrupt request pin with programmable falling or both in falling and rising edge. NMI in in in out Interrupt request pin 0: Interrupt request pin with programmable level or rising-edge. INT0 Address mode pins: These pins are set as following, (Single-Chip mode) AM0 = L, AM1 = H (Single-Boot mode) AM0 = H, AM1 = H Test mode pins: These pins are set as following, (Single Chip & Single Boot mode) TEST0 = L, TEST1 = L Programmable clock output (with pull-up register). Low frequency oscillator connecting pins. Crystal or ceramic resonator is connected. RC oscillation is also possible depending on MASK option. Reset: Initializes LSI (with pull-up register). AD reference voltage high AD reference voltage low Power supply pin for AD converter (+5V): Connect ADVCC pin to 5V power supply. GND pin for AD converter: Connect ADVSS pin to GND (0V). Power supply pins (+5V): Connect all DVCC5 pins to 5V power supply. Power supply pins (+3.3V): Connect all DVCC3 pins to REGOUT pin. GND: Connect all DVSS pins to GND (0V). Regulator output 3.3V: Connect capacitor to stabilize the regulator output. Regulator enable pin: Should be set to H or OPEN (with pull-up register). 37th 80th, 78th 76th, 71st 77th 74th, 72nd 70th, 69th 79th 4th 3rd 2nd 1st 15th, 40th, 50th,61st,75th 36th,68th,86th 13th,38th,51st, 63rd,73rd,88th 49th 52nd 1 2 2 1 2 2 1 1 1 1 1 5 3 6 1 1 in/out Oscillator connecting pins in/out in in in out in 92FD54AI-8 2006-01-27 TMP92FD54AI 3. OPERATION This section describes the basic components, functions and operation of TMP92FD54AI. 3.1 CPU TMP92FD54AI contains an advanced high-speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline 900/H1 CPU is high-speed and high-performance CPU based on 900/H CPU. 900/H1 CPU has expanded 32-bit internal data bus to process Instructions more quickly. Outline of 900/H1 CPU are as follows: 900/H1 CPU 24-bit 32-bit 16 to 20MHz (@fOSC=8 to 10MHz) 1-clock access (50ns@fOSC=10MHz) 32-bit 1-clock access 32-bit interleave 2-1-1-1-clock access 8/16-bit 2-clock access PORT, INTC, MEMC 8/16-bit 5 to 6-clock access SEI, SIO, WDT, 8-bit Timer, 16-bit Timer, RTC, 10-bit ADC, SBI, CAN 8-bit 2-clock access (can insert some waits) 1-clock(50ns@fOSC=10MHz) 2-clock(100ns@fOSC=10MHz) 12-byte Compatible with TLCS-900, 900/H, 900/L, 900/L1 and 900/H2 (NORMAL, MIN, MAX and LDX instruction is deleted) 8-channels Width of CPU Address Bus Width of CPU Data Bus Internal Operating Frequency Minimum Bus Cycle (Internal RAM) Internal RAM Internal ROM Internal I/O External Device Minimum Instruction Execution Cycle Conditional Jump Instruction Queue Buffer Instruction Set Micro DMA 92FD54AI-9 2006-01-27 TMP92FD54AI 4. Functional Description This section describes the hardware configuration of the TMP92FD54AI and how it operates. This device is a modified version of the TMP92CD54I with an internal 512K-byte flash memory instead of an internal 512K-byte Mask ROM. These internal RAM are same size, 32K-byte. In all other respects the hardware configuration and the functionality of the TMP92FD54AI are identical to those of the TMP92CD54I. 4.1 Flash Memory Features 1) Memory capacity TMP92FD54AI contains a 4-Mbit (512K-byte) flash memory. This flash memory consists of 10 blocks (64 K-bytes x 6 blocks, 56 K-bytes x 2 blocks, 8 K-bytes x 2 blocks), each of which can be independently protected from being programmed or erased. The CPU accesses the flash memory using a 32-bit wide data bus. A writer rewrites the flash memory in units of 16 bits. 2) Flash memory access Interleaved access (2-1-1-1-clock access) 3) Program/erase time Programming time (including Verify):6 seconds per chip (typ.) 30 s per long word (typ.) Erase time (including Verify) 12 seconds per chip (typ.) Note: The above values are typical times and do not include data transfer time. The actual time per chip varies according to the method used by the user to perform rewriting. 4.1.1 4) Programming methods On-board programming mode, in which the memory can be rewritten while mounted on the user PCB. * On-board programming mode 1) User Boot M ode Supports user-defined rewriting methods. 2) Single Boot M ode Supports rewriting by serial transfer (unique to Toshiba). 5) Rewriting method With a few exceptions, the functions of the device's internal flash memory conform to JEDEC standards. Therefore, even if the user system uses flash memory as external memory, it can easily be adapted to use this LSI. Furthermore, since the device's flash memory has built-in circuits which can automatically write to the flash memory and erase the chip, the user does not have to code a program to perform the program and erase operations. The Block Protect function, which inhibits writing to or erasing the flash memory, only supports software protection (i.e. protection by a command setting), and does not support hardware protection (i.e. protection by the application of a voltage of 12 V). 92FD54AI-10 2006-01-27 TMP92FD54AI JEDEC-based functions Auto Program Auto Chip Erase Auto Block Erase Data Polling / Toggle Bit Functions which have been changed, added or removed 4.1.2 Block diagram of the flash unit Internal Address Bus Internal Data Bus Internal Control Bus Mode setup pin Mode Control Control ROM Controller / Interleave Control Address Data Flash memory Row Decoder Control Circuit (including automatic sequence control circuit) RDY/BSY output Command Register Address Latch Data Latch Column Decoder / Sense Amp Flash Memory Cell 512 KB Erase Block Decoder Figure 4.1.1 Block diagram of the flash unit 92FD54AI-11 2006-01-27 TMP92FD54AI 4.2 Operation Modes TMP92FD54AI has three operation modes. Table 4.2.1 Operation modes Operation Mode Name Single-Chip Mode Description After a reset the device restarts from the internal flash memory. Single-Chip Mode is further sub-divided into the following two modes: Normal Mode and User Boot Mode. The means for selecting between these two modes can be set by the user as desired. For example, it can be set so that if Port 00 = 1, Normal Mode is selected, and if Port 00 = 0, User Boot Mode is selected. The user application program must in corporate a routine to handle mode switching. The user's application program is executed. The flash memory on the user PCB board is rewritten. After a Reset the device starts up from the internal boot ROM (the mask ROM). The boot ROM has an algorithm which allows memory on the user PCB to be rewritten via the device's serial port. The internal flash memory can be rewritten by connecting the PCB to the external host via TMP92FD54AI's serial port and transferring data using TMP92FD54AI data transfer protocol. Normal Mode User Boot Mode Single Boot Mode Of the modes listed in the table above, there are two operation modes in which the flash memory can be programmed: User Boot Mode and Single Boot Mode. At User Boot Mode (in Single-Chip mode) and Single Boot Mode, the internal flash memory can be rewritten while mounted on the user PCB. These two modes are collectively referred to as On-Board Programming Mode. 92FD54AI-12 2006-01-27 TMP92FD54AI The input pin levels on AM0, AM1, TEST0 and TEST1, which are set externally during a Reset, determine the operation mode - either Single-Chip Mode, Single-Boot Mode. For all operation modes, the CPU will start operating in the selected mode on completion of the reset. The input pin levels are set before the reset is completed. Once the mode has been set, make sure that the input pin levels do not change during operation. The following table shows how each operation mode is set. The state diagram beneath the table shows the various possible mode transitions. Table 4.2.2 Operation mode pin settings Operation Mode RESET (1) (2) Single-Chip Mode (Normal & User Boot) Single Boot Mode AM1 1 1 Input Pins AM0 0 1 TEST1 0 0 TEST0 0 0 Reset state (1) / RESET = 0 (2) / RESET = 0 Single-Chip Mode Single Boot Mode Normal Mode User Boot Mode Switching set by the user On-Board Programming Mode Numbers in ( ) indicate the column row in the above table in which the input pin levels for the mode setting are shown. Figure 4.2.1 Mode transition diagram 4.2.1 Reset operation To reset the device, hold the RESET input Low (= 0) for at least 20 system clock periods while the power supply voltage is within the rated operating range and the internal high-frequency oscillator is oscillating stably. When the device is operating at 20 MHz, this period will by equal to 4 s. For details please refer to the section entitled Reset Operation in TMP92CD54I User's Manual. 92FD54AI-13 2006-01-27 TMP92FD54AI 4.2.2 Memory map for each mode The memory map for the device varies according to the operation mode. The following diagram shows the memory map for each operation mode. Single-Chip Mode 000000H 000400H Internal I/O Internal RAM 32KB Single-Boot Mode 000000H 000400H Internal I/O Internal RAM 32KB 008400H 008400H External memory 010000H External memory () Internal ROM Flash 512KB Flash ROM 090000H External memory F80000H Internal Flash ROM 512KB FFFF00H FFFFFFH (Interrupt vector 256B) FFF000H Reserved FFF400H Internal Boot ROM 3KB FFFF00H FFFFFFH (Interrupt vector 256B) Figure 4.2.2 TMP92FD54AI memory map for each mode Low 64KB 64KB 64KB 64KB Address 512KB 64KB 64KB 56KB 56KB High 8KB 8KB Block-4 Block-5 Block-6 Block-7 Block-8 Block-9 Block-0 Block-1 Block-2 Block-3 Figure 4.2.3 Block allocation 92FD54AI-14 2006-01-27 TMP92FD54AI Table 4.2.3 Block address range by mode Single-Chip Mode Block-0 Block-1 Block-2 Block-3 Block-4 Block-5 Block-6 Block-7 Block-8 Block-9 (64 KB) (64 KB) (64 KB) (64 KB) (64 KB) (64 KB) (56 KB) (56 KB) ( 8 KB) ( 8 KB) F80000H to F8FFFFH F90000H to F9FFFFH FA0000H to FAFFFFH FB0000H to FBFFFFH FC0000H to FCFFFFH FD0000H to FDFFFFH FE0000H to FEDFFFH FEE000H to FFBFFFH FFC000H to FFDFFFH FFE000H to FFFFFFH Single-Boot Mode 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07DFFFH 07E000H to 08BFFFH 08C000H to 08DFFFH 08E000H to 08FFFFH 92FD54AI-15 2006-01-27 TMP92FD54AI 4.3 On-Board Programming Mode (User-Boot and Single-Boot) On-board Programming Mode allows flash memory to be rewritten while it is mounted on the user's target system board. There are two versions of this mode: Single Boot Mode, which supports the Toshiba proprietary method of rewriting via serial I/O, and User Boot Mode (in Single-Chip mode), which allows user-defined rewriting methods to be defined in Single-Chip Mode. 4.3.1 User Boot Mode (in Single-Chip Mode) User Boot Mode enables a user-defined flash memory rewrite routine to be used. This mode is used when the data transfer bus which the user application flash memory rewrite program uses is not serial. Rewriting is performed in Single-Chip Mode. For this reason the operation mode within Single-Chip Mode must be changed, from Normal Mode (the mode in which the user application program normally operates) to User Boot Mode, in which mode the flash memory can be rewritten. This requires that a condition-judging program be incorporated into the user application reset-processing program. Any mode-switching condition may be set using the device's I/Os as long as it is suitable for the user system. Also, the user's exclusive flash memory rewrite routine, for use in User Boot Mode, may be programmed into the user application in advance, so that it can be used to rewrite the flash memory after the device has entered User Boot Mode. Furthermore, since the processor cannot read data from the internal flash memory during an erase/program operation, the rewrite routine must be stored somewhere outside the flash memory so that it can be executed. While the on-chip flash memory is being rewritten in User Boot mode, all interrupts including the non-maskable interrupt must be disabled. The pages which follow explain the procedure for rewriting the flash memory using two example case studies. In one case the rewrite routine is put into the internal flash memory (1-A); in the other the rewrite routine is transferred from an external source (1-B). For details of how to program/erase the flash memory, refer to Section 4.4, Programming/Erasing Flash Memory during on-Board Programming. 92FD54AI-16 2006-01-27 TMP92FD54AI User Boot Mode (1-A) Example procedure in which the rewrite routine is stored in the internal flash memory (Step 1) First, the conditions (e.g. the pin status) under which the program will enter User Boot Mode must be set and the I/O bus which the program will use to transfer data must be selected. Then a circuit must be designed and a corresponding program written. Before mounting this device on the board, the following four programs must be written into one of the blocks of the flash memory using a programmer or similar device. (a) Mode judgment routine: code to determine when rewriting of the device will commence code to read the rewrite data from an external source and then (b) Flash rewrite routine: rewrite the flash memory (c) Copy routine-1: code to copy (a) to (d) into the internal RAM or to external memory (d) Copy routine-2: code to copy (a) to (d) to the flash memory from the internal RAM or the external memory. (Controller) New user application program (TMP92FD54AI) Flash memory Old user application program [Reset-processing program] (a) Mode judgment routine (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 (I/O) RAM (Step 2) The following explanation of the proceeding step assumes that the routines described above have been included in the Reset-processing program. After a Reset the Reset-processing program must first determine whether or not the device should enter User Boot Mode. If the condition for entering User Boot Mode is true, the program must put the device into User Boot Mode, the mode in which the flash memory can be rewritten. (Once the device has entered User Boot Mode, no interrupts not even NMIs should be used.) (Controller) New user application program (TMP92FD54AI) Flash memory Old user application program [Reset-processing program] (a) Mode judgment routine (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 (I/O) 0 1 RESET RAM (c) Copy routine Condition for determining whether or not the device should be put into User Boot Mode (set by the user) 92FD54AI-17 2006-01-27 TMP92FD54AI (Step 3) After the device has entered User Boot Mode, (c), the copy routine, must copy (a) to (d), the flash rewrite routine, into the internal RAM or into external memory. (In the example shown below the routine is copied into the internal RAM.) (Controller) New user application program (TMP92FD54AI) Flash memory Old user application program (I/O) (a) Mode judgment routine [Reset-processing program] (a) Mode judgment routine (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 RAM (Step 4) The program jumps to the rewrite routine in RAM, erases all blocks (chip-erase). (Controller) New user application program (TMP92FD54AI) Flash memory (I/O) (a) Mode judgment routine (Erased) (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 RAM 92FD54AI-18 2006-01-27 TMP92FD54AI (Step 5) The copy routine-2 in the RAM is executed and writes (a) to (d) into the flash memory. (Controller) New user application program (TMP92FD54AI) Flash memory (I/O) (a) Mode judgment routine [Reset-processing program] (a) Mode judgment routine (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 RAM (Step 6) Next, the rewrite routine in the RAM is executed and writes the new user application program into the erased area of the flash memory after loading it from the source of transfer (the controller). (Controller) New user application program (TMP92FD54AI) Flash memory New user application program (I/O) (a) Mode judgment routine [Reset-processing program] (a) Mode judgment routine (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 RAM 92FD54AI-19 2006-01-27 TMP92FD54AI (Step 7) The RESET input pin must be driven Low (= 0) to reset the device and to set it to Normal Mode. After de-assertion of the reset, the processor will start running the new user application program. (Controller) (TMP92FD54AI) Flash memory New user application program [Reset-processing program] (a) Mode judgment routine (b) Flash rewrite routine (c) Copy routine-1 (d) Copy routine-2 (I/O) 0 1 RESET Set to Normal Mode RAM 92FD54AI-20 2006-01-27 TMP92FD54AI (1-B) Example procedure for when the rewrite routine is transferred from an external source. (Step 1) First, the condition (e.g. the pin status) under which the program will enter User Boot Mode must be set and the I/O bus which the program will use to transfer data must be selected. Then a circuit must be designed and a corresponding program written. Before mounting this device on the board, the following two programs must be written into one of the blocks of the flash memory using a programmer or similar device. (a) Mode judgment routine: Code to determine when rewriting of the device will commence (b) Transfer routine: Program for reading the rewrite program from an external source In addition, the programs shown below should be present in the host: (c) Rewrite routine: Program for rewriting the flash memory (d) Copy routine-1: Code to copy (a) to (d) into the internal RAM or to the external ROM. (e) Copy routine-2 Code to copy (a) to (d) into the flash memory from the internal RAM or the external ROM New user application program (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (Controller) (I/O) (TMP92FD54AI) Flash memory Old user application program [Reset-processing program] (a) Mode judgment routine (b) Transfer routine RAM (Step 2) The following explanation of the proceeding step assumes that the routines described above have been included in the Reset processing program. After reset the Reset-processing program must first determine whether or not the device should enter User Boot Mode. If the condition for entering User Boot Mode is true, the program must put the device into User Boot Mode, the mode in which to the flash memory can be rewritten. (Once the device has entered User Boot Mode, no interrupts not even NMIs should be used.) New user application program (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (Controller) (I/O) (TMP92FD54AI) Flash memory Old user application program [Reset-processing program] (a) Mode judgment routine (b) Transfer routine 0 1 RESET RAM Condition for determining whether or not the device should be put into User Boot Mode (set exclusively by the user) 92FD54AI-21 2006-01-27 TMP92FD54AI (Step 3) After the device has entered User Boot Mode, (c) Rewrite routine, (d) Copy routine-1 and (e) Copy routine-2, must be loaded from the source of transfer (the controller) into the internal RAM or into external memory using (b), the transfer routine. (In the example shown below the routine is copied into the internal RAM.) (Controller) (I/O) New user application program (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (TMP92FD54AI) Flash memory Old user application program [Reset-processing program] (a) Mode judgment routine (b) Transfer routine (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 RAM (Step 4) The program jumps to the copy routine-1 in RAM, copy (a) and (b) into the internal RAM or into external memory. (In the example shown below the routine is copied into the internal RAM.). New user application program (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (Controller) (I/O) (TMP92FD54AI) Flash memory Old user application program [Reset-processing program] (a) Mode judgment routine (b) Transfer routine (a) Mode judgment routine (b) Transfer routine (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 RAM 92FD54AI-22 2006-01-27 TMP92FD54AI (Step 5) The rewrite routine in the RAM is executed, erase all block of the flash memory (Chip-erase). (Controller) (I/O) New user application program (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (TMP92FD54AI) Flash memory (a) Mode judgment routine (b) Transfer routine (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (erased) RAM (Step 6) The copy routine-2 in the RAM is executed, copy (a) and (b) into the flash memory. (Controller) (I/O) New user application program (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (TMP92FD54AI) Flash memory (a) Mode judgment routine (b) Transfer routine (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 [Reset-processing program] (a) Mode judgment routine (b) Transfer routine RAM 92FD54AI-23 2006-01-27 TMP92FD54AI (Step 7) Next, the rewrite routine in the RAM is executed and writes the new user application program into the erased area of the flash memory after loading it from the source of transfer (the controller). (Controller) (I/O) New user application program (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 (TMP92FD54AI) Flash memory New user application program [Reset-processing program] (a) Mode judgment routine (b) Transfer routine (a) Mode judgment routine (b) Transfer routine (c) Rewrite routine (d) Copy routine-1 (e) Copy routine-2 RAM (Step 8) The RESET input pin must be driven Low (= 0) to reset the device and to set it to Normal Mode. After de-assertion of the reset, the processor will start running the new user application program. (Controller) (I/O) (TMP92FD54AI) Flash memory New user application program 0 1 RESET Set to Normal Mode [Reset-processing program] (a) Mode judgment routine (b) Transfer routine RAM 92FD54AI-24 2006-01-27 TMP92FD54AI 4.3.2 Single-Boot Mode This mode involves activation of the internal boot ROM (mask ROM) so that the flash memory can be rewritten using a program stored in the boot ROM. In this mode the internal boot ROM is mapped into an area containing the interrupt vector table, in which the boot ROM program is executed. The flash memory is mapped into an address space different from the one into which the boot ROM is mapped (see Figure 4.2.2). In Single-Boot Mode the flash memory is rewritten by serial transfer of commands and data. First, the device's SIO (SIO1) and the external host are connected and the rewrite program is copied from the external host into the device's internal RAM; the rewrite program is then executed in RAM and the flash memory rewritten. The rewrite routine is initiated by sending commands and rewrite data from the host. The device must communicate with the host following the protocol described later. Before the program can be transferred into RAM, the user password is checked to ensure the security of the user ROM data. If the password does not match, the program is not transferred into RAM. Interrupts must be disabled when peripheral functions such as the SIO is utilized in Single Boot mode. Nonetheless, the code for an interrupt cause is recorded in the INTES1 register ; thus, for example, data receptions or transmissions in the SIO can be confirmed by keeping track of value changes of the INTES1 register. The NMI interrupt must be disabled at this time. To prevent the contents of flash memory inadvertently rewritten in Single-Chip Mode (Normal Mode), it is recommended that, on completion of rewriting, write-protect be set for any blocks which the user wishes to protect. For details of how to program/erase the flash memory, please refer to Section 4.4, Programming/Erasing Flash Memory during On-Board Programming. 92FD54AI-25 2006-01-27 TMP92FD54AI Single Boot Mode (2-A) Using the rewrite algorithm in the internal boot ROM (Step 1) The state of the flash memory is not important; it may contain the old version of the user program or it may have been erased. Since the rewriting routine and rewrite data are transferred via SIO (SIO1), the device's SIO (SIO1) and the external controller should be connected on the board. The user must ensure that (a), the rewrite routine, is present on the controller. (Controller) (I/O) New user application program (a) Rewrite routine (TMP92FD54AI) Boot ROM Flash memory SIO1 Contains old user application program (or has been erased). RAM (Step 2) To turn the boot ROM on, Reset must be de-asserted by setting the input pins accordingly. (a), the rewriting routine, must be transferred from the source (the controller) into the device via SIO. Before this is carried out, however, the password entered by the user must be checked against the password registered on the user application program. (When the flash memory has been erased, erase data ("0xFF"12byte ) is used as the password.) (Controller) (I/O) New user application program (a) Rewrite routine 0 1 RESET (TMP92FD54AI) Boot ROM Flash memory SIO1 Old user application program (or erased) RAM 92FD54AI-26 2006-01-27 TMP92FD54AI (Step 3) After the password has been checked, (a), the rewrite routine, must be transferred from the source (the controller). The boot ROM then loads the routine into the internal RAM. It must be ensured, however, that the routine is stored within the RAM address area 000400H to 006BFFH. (Controller) (I/O) New user application program (a) Rewrite routine (TMP92FD54AI) Boot ROM Flash memory SIO1 Old user application program (or erased) (a) Rewrite routine RAM (Step 4) The CPU jumps to (a), the rewrite routine, in RAM and the rewrite routine erases the old user application program area (all the blocks at once). (Controller) (I/O) New user application program (a) Rewrite routine (TMP92FD54AI) Boot ROM Flash memory (a) Rewrite routine Erased RAM SIO1 92FD54AI-27 2006-01-27 TMP92FD54AI (Step 5) Next, the Rewrite routine in the RAM is executed and writes the new user application program into the erased area of the flash memory after loading it from the source of transfer (the controller). When the processor has finished writing the new user application program, write-protect for the user program area should be turn on. In the example below the rewrite data is transferred from the same host via the same SIO as the rewrite routine. However, once normal program operation has started in RAM, any other data bus and any other transfer source may be used as desired. The user must design the board hardware and write the rewrite routine accordingly. (Controller) (I/O) New user application program (a) Rewrite routine (TMP92FD54AI) Boot ROM Flash memory (a) Rewrite routine SIO1 New user application program RAM (Step 6) When writing to the device has been completed, turn the power to the board off and remove the cable connecting the device and host. To execute the new user application program, turn the power back on again and start the device in Single-Chip Mode (Normal Mode). (Controller) (TMP92FD54AI) Boot ROM Flash memory SIO1 0 1 RESET New user application program RAM Set for Single-Chip Mode (Normal Mode) 92FD54AI-28 2006-01-27 TMP92FD54AI (1) Typical connection scheme for Single Boot Mode In Single Boot Mode the flash memory is rewritten by means of a serial transfer. Therefore on-board programming is carried out by connecting the device's SIO (Channel1) and the controller (the programming tool) and sending commands from the controller to the target board. Figure 4.3.1 shows an example connection scheme for a programming controller and a target board. Note) Programming controller VCC VCC Target board Supply Voltage Reg. VCC (5 V) Reg. MCU Mode Control for prog. controller DVCC (5 V) AM1 (78 pin) DVcc (3.3 V) RESET Mode Control for AM0 Boot Mode Selection Circuit RESET (79 pin) AM0 (80 pin) ROM RAM MCU RX TX RS232C VSS RXD1 (8 pin) TXD1 (9 pin) TEST1 (71 pin) TEST0 (76 pin) DVSS PC Figure 4.3.1 Example of connection board and external controller in Single Boot Mode (with communication via UART) 92FD54AI-29 2006-01-27 TMP92FD54AI (2) Mode settings Before on-board programming can be performed, the device must be started up in Single Boot Mode. The input pins must be set as follows in order to start the device up in Single Boot Mode. AM0 AM1 TEST0 TEST1 =1 =1 =0 =0 =01 RESET Set the RESET input pin Low (= 0) and set the AM0, AM1, TEST0 and TEST1 pins as shown above. Then de-assert RESET (i.e. set it to 1). The device will start up in Single Boot Mode. (3) Memory map Figure 4.3.2 compares the memory maps for Single-Chip Mode and Single-Boot Mode. As shown, in Single-Boot Mode the internal flash memory is mapped into 010000H to 08FFFFH. The boot ROM (mask ROM) is mapped into FFF400H to FFFFFFH. Single-Chip Mode 000000H 000400H Internal I/O Internal RAM 32KB 000000H 000400H Single-Boot Mode Internal I/O Internal RAM 32KB 008400H 008400H External Memory 010000H External Memory () Internal ROM Flash 512KB Flash ROM 090000H F80000H External Memory Internal Flash ROM 512KB FFFF00H FFFFFFH (Interrupt vector 256B) FFF000H Reserved FFF400H Internal Boot ROM 3KB FFFF00H FFFFFFH (Interrupt vector 256B) Figure 4.3.2 Memory maps for Single-Chip Mode and Single-Boot Mode 92FD54AI-30 2006-01-27 TMP92FD54AI (4) Interface specifications SIO communication specifications for Single Boot Mode are shown below. The device supports a serial operation mode: UART (Asynchronous). Before on-board programming can be executed, the programming controller must be set to the same communications format as the device side. * Communicating in UART Mode Communications channel: SIO Channel1 Serial transfer mode: UART (Asynchronous) Mode, full-duplex communication Data length: 8 bits Parity bits: None STOP bits: 1 Baud rate: Desired baud rate (See Table 4.3.1(a) ) Table 4.3.1(a) Baud Rate (bps) 38400 Baud Rate Selection Table 19200 9600 4800 2400 Table 4.3.1(b) Pin connections Pin Power supply pins Mode-setting pin Reset pin Communications pins DVCC (3.3 V) DVSS AM1, AM0, TEST1, TEST0 UART RESET TXD1 RXD1 (5) Data transfer format The operation commands and data transfer formats for each operation mode are shown in Table 4.3.2 to Table 4.3.67. For related information please refer to subsection (6), entitled Boot program, on page 37 of Section 4.3.2, Single-Boot Mode. Table 4.3.2 Operation command data Operation Command Data 10H 20H 30H 40H Operation Mode RAM transfer Flash memory SUM Read product information Auto Chip Erase & UnProtect 92FD54AI-31 2006-01-27 TMP92FD54AI Table 4.3.3 Single Boot program transfer format (for RAM transfer) Number of bytes transferred BOOT ROM 1st byte Data transferred from the controller to the device Baud rate Data transferred from the device to the controller 2nd byte Serial operation mode and baud rate Desired baud rate (Table settings For UART 86H 4.3.1(a)) 3rd byte 4rth byte Operation command data (10H) 5th byte 16th byte 17th byte 18th byte PASSWORD data (12 bytes) (08FEF4H to 08FEFFH) CHECKSUM value for bytes 5 to 16 ACK response for Serial Operation Mode For UART If normal (can be set) 86H (If the device determines that the baud rate cannot be set, it will stop operating.) ACK response for operation command *1 If normal 10H x 1H If abnormal If communications error occurs x 8H 19th byte 20th byte 21st byte 22nd byte 23rd byte 24th byte 25th byte 26th byte RAM storage start address 31 to 24 RAM storage start address 23 to 16 RAM storage start address 15 to 8 RAM storage start address 7 to 0 RAM storage bytes 15 to 8 RAM storage bytes 7 to 0 CHECKSUM value for bytes 19 to 24 27th byte mth byte (m + 1) th byte (m + 2) th byte RAM storage data ACK response to CHECKSUM value *1 If normal 10H If abnormal 11H If communications error occurs 18H ACK response for CHECKSUM value *1 If normal 10H If abnormal 11H If communications error occurs 18H CHECKSUM value for bytes 27 to m RAM (m + 3) th byte ACK response for CHECKSUM value *1 If normal 10H If abnormal 11H If communications error occurs 18H JUMP RAM storage start address *1: After returning an abnormal response the device waits for the operation command (third byte). In I/O Interface Mode this ACK response is not generated. *2: Write your program so that the data in bytes 19 to 25 is stored within the RAM address area 000400H to 0083FFH. 92FD54AI-32 2006-01-27 TMP92FD54AI Table 4.3.4 Boot program transfer format (for flash memory SUM) Number of bytes transferred BOOT ROM 1st byte Data transferred from the controller to the device Serial operation mode and baud rate settings For UART 86H Baud rate Data transferred from the device to the controller Desired baud rate (Table 4.3.1(a)) 2nd byte 3rd byte 4th byte Operation command data (20H) 5th byte 6th byte 7th byte 8th byte (Wait for the next operation command.) ACK response for Serial Operation Mode For UART If normal (can be set) 86H (If the device determines that the baud rate cannot be set, it will stop operating.) ACK response for operation command *1 If normal 20H If abnormal X1H If communication error occurs X8H SUM (upper) SUM (lower) CHECKSUM value for bytes 5 to 6 *1: After returning an abnormal response the controller waits for the operation command (third byte). 92FD54AI-33 2006-01-27 TMP92FD54AI Table 4.3.5 Boot program transfer format (for reading product information) (1/2) Number of bytes transferred BOOT ROM 1st byte Data transferred from the controller to the device Baud rate Data transferred from the device to the controller 2nd byte Serial operation mode and baud rate Desired baud rate (Table settings For UART 86H 4.3.1(a)) 3rd byte 4th byte Operation command data (30H) 5th byte 6th byte 7th byte 8th byte 9th byte 20th byte 21st byte 24th byte 25th byte 28th byte 29th byte 32nd byte 33rd byte 36th byte 37th byte 44th byte 45th byte 46th byte 47th byte 50th byte 51st byte 54th byte 55th byte 56th byte 57th byte 60th byte ACK response for Serial Operation Mode For UART If normal (can be set) 86H (If the device determines that the baud rate cannot be set, it will stop operating.) ACK response for operation command *1 If normal 30H If abnormal X1H If communication error occurs X8H Flash memory data (address 08FEF0H) Flash memory data (address 08FEF1H) Flash memory data (address 08FEF2H) Flash memory data (address 08FEF3H) Product name (ASCII code, 12 bytes) "TMP92FD54AI " beginning at the 9th byte Password comparison start address (4 bytes) F4H, FEH, 08H and 00H beginning at the 21st byte RAM start address (4 bytes) 00H, 04H, 00H and 00H beginning at the 25th byte RAM user area end address (8 bytes) FFH, 6BH, 00H and 00H beginning at the 29th byte RAM end address (4 bytes) FFH, 83H, 00H and 00H beginning at the 33rd byte Dummy data (8 bytes) 00H, 00H, 00H and 00H 00H, 00H, 00H and 00H Dummy data (2 bytes) 00H and 03H beginning at the 45th byte Flash memory start address (4 bytes) 00H, 00H, 01H and 00H beginning at the 47th byte Flash memory end address (4 bytes) FFH, FFH, 08H and 00H beginning at the 51st byte Flash memory block divisions information (2 bytes) 0AH and 00H beginning at the 55th byte Start address of flash memory block of the same size (4 bytes) 00H, 00H, 01H and 00H beginning at the 57th byte 92FD54AI-34 2006-01-27 TMP92FD54AI Table 4.3.6 Boot program transfer format (for reading product information) (2/2) Number of bytes transferred BOOT ROM 61st byte 64th byte 65th byte 66th byte 69th byte 70th byte 73rd byte 74th byte 75th byte 78th byte 79th byte 82nd byte 83rd byte 84th byte 85th byte Data transferred from the controller to the device Baud rate Data transferred from the device to the controller Size (in half words) of flash memory blocks of the same size (4 bytes) 00H, 80H, 00H and 00H beginning at the 61st byte Number of flash memory blocks of the same size (1 byte) 06H Start address of flash memory block of the same size (4 bytes) 00H, 00H, 07H and 00H beginning at the 66th byte Size (in half words) of flash memory block of the same size (4 bytes) 00H, 70H, 00H and 00H beginning at the 70th byte Number of flash memory blocks of the same size (1 byte) 02H Start address of flash memory block of the same size (4 bytes) 00H, C0H, 08H and 00H beginning at the 75th byte Size (in half words) of flash memory block of the same size (4 bytes) 00H, 10H, 00H and 00H beginning at the 79th byte Number of flash memory blocks of the same size (1 byte) 02H CHECKSUM value for bytes 5 to 83 (Wait for the next operation command data) *1: After returning abnormal response, the device waits for the operation command (third byte). 92FD54AI-35 2006-01-27 TMP92FD54AI Table 4.3.7 Boot program transfer format (for Auto Chip Erase & UnProtect) Number of bytes transferred BOOT ROM 1st byte Data transferred from the controller to the device Serial operation mode and baud rate settings For UART 86H Baud rate Data transferred from the device to the controller Desired baud rate (Table 4.3.1(a)) 2nd byte 3rd byte 4th byte Operation command data (40H) 5th byte 6th byte 7th byte (Wait for the next operation command.) ACK response for Serial Operation Mode For UART If normal (can be set) 86H (If the device determines that the baud rate cannot be set, it will stop operating.) ACK response for operation command *1 If normal 40H If abnormal X1H If communication error occurs X8H Erase Operation result response data If normal 4FH If abnormal 4CH ACK response If normal B1H If abnormal B4H *1: After returning an abnormal response the controller waits for the operation command (third byte). 92FD54AI-36 2006-01-27 TMP92FD54AI (6) Boot program When the device is turned on in Single Boot Mode, the boot program starts up. These functions are detailed in the explanations "1, RAM Transfer command" to "4, Auto Chip Erase & UnProtect command) on the following pages. 1. RAM Transfer command RAM transfer refers to the storing of data received from the controller in the device's internal RAM. If the transfer terminates normally, the boot program will start running the user program. The maximum size of the user program is 26Kbytes, and the address at which program execution starts is the RAM storage start address. This RAM transfer function allows unique on-board programming by executing a rewrite program created by the user. In order for on-board programming to be executed as part of the user program, the flash memory command sequence described later in Section 4.5 must be used. The RAM transfer command examines the result of the password matching check before it starts operation. If the password is found not to match, RAM transfer is not performed. Once the RAM transfer command has been completed, access to the entire on-chip RAM is free. 2. Flash Memory SUM command This command calculates the sum of 512 Kbytes of flash memory and returns the result. There is no operation command available to the boot program which will enable it to read data from the entire area of the flash memory. Instead, this flash memory SUM command must be used. Reading SUM enables revision management of the application program to be carried out. Product Information Read command This command returns the product name, information about the device's memory and various other details. Specifically, this command returns data from a part of the flash memory area (addresses 08FEF0H to 08FEF3H). Using this data as well as the above Flash Memory SUM command enables revision management of the application program to be carried out. 3. 4 Auto Chip Erase & UnProtect command This command erases all the blocks of flash memory. Even when protect function is effective, all the blocks of flash memory are erased and protect function is initialized. It is not necessary to perform comparison of a password in this operation. 92FD54AI-37 2006-01-27 TMP92FD54AI 1) RAM Transfer command (See Table 4.3.3.) 1. The data in the first byte is used to set the serial operation mode. For details of how to set the serial operation mode, please refer to part 6), entitled Determination of Serial Operation mode, on page 47 of subsection 4.3.2 (6), Boot program. If the serial operation mode is found to be UART Mode, the device checks to see if the baud rate can be set. So UART receiving function needs to be disabled (SC1MOD0 2. The data in the second byte is the ACK response returned by the device for the serial operation mode which is set by the data in the first byte. If the data in the first byte is found to signify UART Mode and the baud rate can be set, the device will return 86H. * UART Mode The device checks to see if the baud rate can be set. If it is found that the baud rate can be set, the device rewrites the BR1CR and BR1ADD registers and returns 86H. If it is found that the baud rate cannot be set, the device stops operation and hence does not send any information. The controller sets a time-out time (5 seconds) after it has finished sending the first byte of data. If the data (86H) cannot be received normally within the time-out time, the device should be considered unable to communicate. Reception is enabled (SC1MOD0 3. The data received in the third byte is the operation command data. In this case it is the data for the RAM Transfer command (10H). The data in the fourth byte is the ACK response data returned by the device for the operation command data in the third byte. The first, the device checks if the received data in the third byte contains an error. If a Receive error is found, the device returns the ACK response data for a Communications error (bit 3) X8H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) Next, if the data received in the third byte corresponds to one of the operation command values given in Table 4.3.2, the device echoes back the received data (the ACK response data for normal reception). In this case the data value 10H is echoed back and the program branches to the RAM transfer processing routine. After branching to this routine, the device checks the data in the password area. For details of how to check the data in the password area, refer 4. 92FD54AI-38 2006-01-27 TMP92FD54AI to part 7), entitled The password, on page 50 of subsection 4.3.2 (6), Boot program. If the received data does not correspond to any operation command, the device returns the ACK response data for an Operation Command error (bit 0) X1H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) 5. The data received in bytes 5 to 16 is password data (12 bytes). The data in bytes 5 to 16 is compared with the data in flash memory address 08FEF4H to 08FEFFH respectively. If the password does not match, the device sets the Password Error flag. The data received as the 17th byte is checksum data. For details of how to calculate CHECKSUM data, please refer to part 9), entitled Calculating CHECKSUM, on page 51 of subsection 4.3.2 (6), Boot program. The checksum sent by the controller should be equal to the 2's complement of the unsigned 8-bit value obtained by summing the value of bytes 5 to 16, ignoring any overflow. The data in the 18th byte is the ACK response data returned by the device for the data received as bytes 5 to 17 (the ACK response for the CHECKSUM value). The device first checks to see whether the data received as bytes 5 to 17 contains any Receive errors. If a Receive error is found, the device returns the ACK response data for a Communications error (bit 3) 18H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are the four high-order bits of the immediately preceding operation command data, so the value of these bits is always 1. Next, the device checks the CHECKSUM data in the 17th byte. This check is made to see if the low-order 8-bit value obtained by adding eight bits of the transmission data to bytes 5 to17 not including the sign (ignoring overflow) is 00H. If the value is not 00H, the device returns the ACK response data for a CHECKSUM error (bit 0) 11H and waits for the next operation command (third byte). Finally, the device examines the result of the password matching check. In the following cases the device returns ACK response data for a Password error (bit 0) 11H and waits for the next operation command (third byte). * Irrespective of the result of the password matching check for bytes 5 to 17, all 12 bytes of data in the password area will have the same value (a value other than FFH). None of the password data in bytes 5 to 17 matches the corresponding flash memory data. 6. 7. * If all data is found to be normal as a result of the above check, the device returns the ACK response data for normal reception, 10H. 8. The data received as bytes 19 to 22 indicates the start address in RAM in 92FD54AI-39 2006-01-27 TMP92FD54AI which the block-transferred data is to be stored. The 19th byte corresponds to address bits 31 to 24 and the 22nd byte corresponds to address bits 7 to 0. 9. The data received as bytes 23 to 24 as bytes 19 to 22 the number of block-transferred bytes. The 23rd byte corresponds to bits 15 to 8 and the 24th byte to bits 7 to 0 of the transfer byte count. 10. The data received as the 25th byte is checksum data. The checksum data sent by the controller should be equal to the 2's complement of the unsigned 8-bit value obtained by summing the values of bytes 19 to 24 ignoring any overflow. For details of how to calculate checksum data, please refer to part 9), entitled Calculating CHECKSUM, on page 51 of subsection 4.3.2 (6), Boot program. 11. The data in the 26th byte is the ACK response data returned by the device for the data received as bytes 19 to 25 (the ACK response for CHECKSUM value). The device first checks to see whether the data received as bytes 19 to 25 contains any Receive errors. If a Receive error is found, the device returns the ACK response data for a Communications error (bit 3) 18H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are the four high-order bits of the immediately preceding operation command data, so the value of these bits is always 1. Next, the device checks the CHECKSUM data in the 25th byte. This check is made to see if the low-order 8-bit value obtained by adding eight bits of the transmission data to bytes 19 to 25 not including the sign (ignoring overflow) is 00H. If the value is not 00H, the device returns the ACK response data for a CHECKSUM error (bit 0) 11H and waits for the next operation command (third byte). * Write your program so that the data in bytes 19 to 25 are stored within a RAM address area from 000400H to 006BFFH. If all data is found to go normal as a result of the above check, the device returns the ACK response data for normal reception, 10H. 12. The data received as bytes 27 to m is the data which is to be stored in RAM. This data is written to RAM starting at the start address specified by the data received as bytes 19 to 22 and up until the number of bytes specified by the data received as bytes 23 to 24 in the 23rd to the 24th bytes has been reached. 13. The data received as the m + 1'th byte is checksum data. The checksum sent by the controller should be equal to the 2's complement of the unsigned 8-bit value obtained by summing the values of bytes 27 to m, ignoring any overflow. For details of how to calculate checksum data, please refer to part 9), entitled Calculating CHECKSUM, on page 51 of subsection 4.3.2 (6), Boot program. 14. The data in the m + 2'th byte is the ACK response data returned by the device for the data received as bytes 27 to m + 1 (the ACK response for the CHECKSUM value). The device first checks to see whether the data received as bytes 27 to m + 1 contains any Receive error. If a receive error is found, the 92FD54AI-40 2006-01-27 TMP92FD54AI device returns the ACK response data for a Communications error (bit 3) 18H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are the four high-order bits of the immediately preceding operation command data, so the value of these bits is always 1. Next, the device checks the checksum data in the m + 1'th byte. This check is made to see whether the low-order 8-bit value obtained by adding eight bits of the transmission data to 27 to m + 1 bytes not including the sign (ignoring overflow) is 00H. If the value is not 00H, the device returns the ACK response data for a CHECKSUM error (bit 0) 11H and waits for the next operation command (third byte). If all data is found to be normal as a result of the above check, the device returns the ACK response data for normal reception, 10H. 15. If the ACK response data in the (m + 2)th byte is a normal ACK response, the device sends the normal ACK response data 10H and then branches to the address specified by the data received as bytes 19 to 22. 92FD54AI-41 2006-01-27 TMP92FD54AI 2) Flash Memory SUM command (See Table 4.3.4.) 1. The transmitted/received data in the first and second bytes are the same as for the RAM Transfer command. The data received in the third byte is the operation command data. In this case it is flash memory SUM command data (20H). The data in the fourth byte is the ACK response data returned by the device for the operation command data in the third byte. The first, the device checks if the received data in the third byte contains an error. If a Receive error is found, the device returns the ACK response data for, Communication error (bit 3) X8H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) Next, if the data received in the third byte corresponds to one of the operation command values given in Table 4.3.2, the device echoes back the received data (the ACK response data for normal reception). In this case the data value 20H is echoed back and the program branches to the flash memory SUM processing routine. If the received data does not correspond to any operation command the device returns the ACK response data for an Operation Command error (bit 0) X1H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) 4. The data in the fifth and the sixth bytes sent by the device are the high-order and the low-order SUM data respectively. For details of how to calculate SUM, please refer to part 8), entitled Calculating SUM, on page 51 of subsection 4.2.2 (6), Boot program. The data in the seventh byte sent by the device is CHECKSUM data. This is the low-order 8-bit value in 2's complement representation obtained by adding eight bits of transmit data in the fifth to the sixth bytes not including the sign (ignoring overflow). The data received as the eighth byte is the data value for the next operation command. 2. 3. 5. 6. 92FD54AI-42 2006-01-27 TMP92FD54AI 3) Product Information Read command (See Table 4.3.5.) 1. The transmitted/received data in the first and second bytes are the same as for the RAM Transfer command. The data received in the third byte is the operation command data. In this case it is product information read command data (30H). The data in the fourth byte is the ACK response data returned by the device for the operation command data in the third byte. The first, the device checks if the received data in the third byte contains an error. If a Receive error is found, the device returns ACK response data for a Communication error (bit 3) X8H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) Next, if the data received in the third byte corresponds to one of the operation command values given in Table 4.3.2, the device echoes back the received data (the ACK response data for normal reception). In this case the data value 30H is echoed back, and the program branches to the product information read processing routine. If the received data does not correspond to any operation command data, the device returns the ACK response data for an Operation Command error (bit 0) X1H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) 4. The data in bytes 5 to 8 sent by the device is flash memory data (the data at addresses 08FEF0H to 08FEF3H). These addresses can be used to write ID information for the software, facilitating version management. The data in bytes 9 to 20 sent by the device denotes the product name. This data is "TMP92FD54AI" and is transmitted as a sequence of ASCII codes starting from the ninth byte. The data in bytes 21 to 24 sent by the device is the password comparison start address. This data consists of the values F4H, FEH, 08H and 00H and is transmitted starting from the 21st byte. The data in bytes 25 to 28 sent by the device is the RAM start address. This data consists of the values 00H, 04H, 00H and 00H and is transmitted starting from the 25th byte. 2. 3. 5. 6. 7. 8. The data in bytes 29 to 32 sent by the device is the RAM user area end address. This data consists of the values 006BFFH and is transmitted starting from the 29th byte. 9. The data in bytes 33 to 36 sent by the device is the RAM end address. This data consists of the values FFH, 83H, 00H and 00H and is transmitted starting from the 33rd byte. 92FD54AI-43 2006-01-27 TMP92FD54AI 10. The data in bytes 37 to 44 sent by the device is the dummy data. 11. The data in bytes 45 to 46 sent by the device is the dummy data 12. The data in bytes 47 to 50 sent by the device is the flash memory start address. This data consists of the values 00H, 00H, 01H and 00H and is transmitted starting from the 47th byte. 13. The data in bytes 51 to 54 sent by the device is the flash memory end address. This data consists of the values FFH, FFH, 08H and 00H and is transmitted starting from the 51st byte. 14. The data in bytes 55 to 56 sent by the device is the data which indicates how many blocks the flash memory is divided into. This data consists of the values 0AH and 00H and is transmitted starting from the 55th byte. 15. The data in bytes 57 to 92 sent by the device is the data containing information on flash memory blocks. With consecutive blocks of a given size starting at the flash memory start address comprising one unit, this information gives the start address of the first block, the size of the block (in half words) and the number of blocks in each unit of a given size. The data in bytes 57 to 65 sent by the device gives the above information for the 64K-byte blocks (Block 0 to Block 5). Similarly, the data in bytes 66 to 74 gives the information for the 56K-byte blocks (Block 6 and Block 7), the data in bytes 75 to 83 gives the information for the 8-Kbyte blocks (Block 8 and Block 9). For a description of this data, please refer to Table 4.3.5. 16. The data in the 84th byte sent by the device is checksum data. This is the low-order 8-bit value in 2's complement representation obtained by adding eight bits of transmit data in the fifth to the 83rd bytes not including the sign (ignoring overflow). 17. The received data in the 85th byte is the next operation command data. 92FD54AI-44 2006-01-27 TMP92FD54AI 4) Auto Chip Erase & UnProtect command (See Table 4.3.47.) 1. The transmitted/received data in the first and second bytes are the same as for the RAM Transfer command. The data received in the third byte is the operation command data. In this case it is Auto Chip Erase & UnProtect command data (40H). The data in the fourth byte is the ACK response data returned by the device for the operation command data in the third byte. The first, the device checks if the received data in the third byte contains an error. If a Receive error is found, the device returns the ACK response data for, Communication error (bit 3) X8H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) Next, if the data received in the third byte corresponds to one of the operation command values given in Table 4.3.2, the device echoes back the received data (the ACK response data for normal reception). In this case the data value 40H is echoed back and the program branches to the Auto Chip Erase & UnProtect processing routine. If the received data does not correspond to any operation command the device returns the ACK response data for an Operation Command error (bit 0) X1H and waits for the next operation command (third byte). The four high-order bits of the returned ACK response data are undefined. (They are the four high-order bits of the immediately preceding operation command data.) 4. The data in the fifth bytes sent by the device indicates whether collective erase has terminated normally. When collective erase has terminated normally, the device returns collective erase terminated normally code (4FH). If an erase error occurs, the device returns erase error code (4CH). 5. The data in the sixth bytes sent by the device are ACK response data. When collective erase has terminated normally, the device returns collective erase ACK response code (B1H). If an erase error occurs, the device returns erase error ACK response code (B4H). 6. The data received as the seventh byte is the data value for the next operation command. 2. 3. 92FD54AI-45 2006-01-27 TMP92FD54AI 5) ACK response data The boot program notifies the controller of the processing status by sending various codes. Table 4.3.8 to Table 4.3.101 show the ACK response data returned by the device for each item of received data. The four high-order bits of the ACK response data are a direct reflection of the four high-order bits of the operation command data. Bit 3 indicates a Receive error, and bit 0 indicates an Operation Command error, CHECKSUM error or Password Error. Bits 1 and 2 are always 0. Table 4.3.8 ACK response data to data for determining the serial operation mode Returned Data 86H Meaning of Data Returned by the Device It is found that device can communicate in UART Mode. Table 4.3.9 ACK response data to operation command data Returned Data x8H *1 x1H *1 10H 20H 30H 40H Meaning of Data Returned by the Device A Receive error occurred in the operation command data. Undefined operation command data was received normally. Data was found to be a RAM Transfer command. Data was found to be a Flash Memory SUM command. Data was found to be a Product Information Read command. Data was found to be an Auto Chip Erase & UnProtect command. *1: The four high-order bits are a direct reflection of the four high-order bits of the immediately preceding operation command data. Table 4.3.10 ACK response data to CHECKSUM data Returned Data 18H 11H 10H Meaning of Data Returned by the Device An error had occurred in the received data. A CHECKSUM error or password error occurred. The CHECKSUM was found to be the correct value. Table 4.3.11 ACK response data to Auto Chip Erase & UnProtect data Returned Data 4FH 4CH B1H B4H Meaning of Data Returned by the Device The erase operation has terminated normally The erase error occurred. Reconfirmation of erase operation Reconfirmation of erase error operation 92FD54AI-46 2006-01-27 TMP92FD54AI 6) Determination of Serial Operation mode When communicating in UART Mode, the controller should transmit the data value 86H as the first byte at the desired baud rate. Start Point A UART (86H) bit 0 bit 1 Point B bit 2 bit 3 Point C bit 4 bit 5 bit 6 bit 7 Point D Stop tAB tCD Figure 4.3.3 Data for determining the serial operation mode The boot program disables reception of the serial operation method recognition data (86H) received from the controller as the first byte after a Reset and finds the durations of tAB, tAC and tAD shown in Figure 4.3.3 using the procedure shown in the flowchart in Figure 4.3.4. As shown in the flowchart in Figure 4.3.4, when the CPU detects a level change on the receive pin while monitoring the pin status, it latches the current timer value. For this reason, the timer values for tAB, tAC and tAD are somewhat erroneous. Also, if the baud rate is fast, the CPU may not be able to detect a level change on the receive pin. As shown in the flowchart in Figure 4.3.5, the serial operation mode is determined by the relative magnitude of the durations tAB and tCD when the receive pin level is Low. When tAB < tCD, the serial operation mode is found to be UART Mode and the boot program determines from the duration of tAD whether or not the baud rate can be automatically set. Since the timer values for tAB, tAC and tAD include some error, as mentioned earlier, if the baud rate is fast and the operating frequency slow, the timer values will not be long enough to enable the boot program to determine the serial operation mode correctly as intended. For example, it may be erroneously determined that the serial operation mode is not UART Mode when in fact the controller intends to communicate in UART Mode. To avoid this kind of problem, if the controller is trying to communicate in UART Mode, a time-out time after transmission of the first byte of data should be set for the controller; if the data 86H cannot be received normally from the device within the time-out time, this can be used to determine that the device cannot communicate. 92FD54AI-47 2006-01-27 TMP92FD54AI Start Initialize 16-bit Timer 0 (T1 = 8/f, counter cleared) Set TB0RG1 value = 0xFFFF Prescaler starts Point A Receive pin changed from High to Low? YES 16-bit Timer 0 starts counting up Point B Receive pin changed from Low to High? YES Latch and save timer value using soft capture (tAB) Point C Receive pin changed from High to Low? YES Latch and save timer value using soft capture (tAC) NO Point D Receive pin changed from Low to High? YES Latch and save timer value using soft capture (tAD) 16-bit Timer 0 stops counting NO tAC tAD? YES NO Back up tAD value Stop operation (infinite loop) End Figure 4.3.4 Serial operation mode reception flowchart 92FD54AI-48 2006-01-27 TMP92FD54AI Start tCD tAD - tAC tAB > tCD? NO Found to be UART Mode YES Error Figure 4.3.5 Flowchart for determination of serial operation mode 92FD54AI-49 2006-01-27 TMP92FD54AI 7) The password If the received operation command data is a RAM Transfer command (10H), the boot program checks the password. First, after echoing back the received operation command data (10H), the boot program checks the data (12 bytes) in the password area (addresses 08FEF4H to 08FEFFH). Next, the boot program checks the received data in bytes 5 to 16 (the password data) against the corresponding data in the flash memory. The relationship between the received data and the flash memory data which is compared with it is shown in Table 4.3.5. Unless all of 12 bytes of the data match, a Password error is assumed to have occurred. In this case, the ACK response returned for the CHECKSUM value in the 17th byte will signify a Password error. Table 4.3.12 Relationship between data received and data in flash memory with which it is compared Received Data 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte 16th byte Flash Memory Data for Comparison Data at address 08FEF4H Data at address 08FEF5H Data at address 08FEF6H Data at address 08FEF7H Data at address 08FEF8H Data at address 08FEF9H Data at address 08FEFAH Data at address 08FEFBH Data at address 08FEFCH Data at address 08FEFDH Data at address 08FEFEH Data at address 08FEFFH 92FD54AI-50 2006-01-27 TMP92FD54AI 8) Calculating SUM SUM is word value which the boot program returns after summing the values of all the data bytes which it has read. The resulting SUM is sent to the controller high-order byte first and low-order byte last. All the data in the flash memory (512 K-bytes) is included in the calculation of SUM. The following example illustrates how the flash memory SUM command calculates the SUM value which is returned. Example: When the calculation is performed on the four data entries shown on the left, the value of SUM is: A1H + B2H + C3H + D4H = 02EAH Hence the high-order data value for SUM is 02H and the low-order data value is EAH. Therefore SUM is sent to the controller as the value 02H followed by the value EAH. A1H B2H C3H D4H 9) Calculating CHECKSUM CHECKSUM is obtained by taking the 2's-complement of the unsigned 8-bit value obtained by summing the values of the bytes received, ignoring any overflow. The CHECKSUM returned when the Flash Memory SUM command or Product Information Read command is executed is calculated in this way. The controller should also use this calculation method when transmitting CHECKSUM values. Example: Calculating CHECKSUM for Flash Memory SUM command In this example the CHECKSUM value is found for when the high-order byte of SUM is E5H and the low-order byte is F6H. First, the bytes are summed to yield an unsigned result. E5H + F6H = 1DBH Take the 2s complement of the low-order byte of the resulting value as shown below. The result is the CHECKSUM value. Consequently, the value 25H is sent to the controller. 0 - DBH = 25H 92FD54AI-51 2006-01-27 TMP92FD54AI (7) Boot program general flowchart Figure 4.3.6 shows an overall flowchart for the boot program. Single boot program starts Initialize Enter SIO Operation Mode data UART Baud rate setting? Can be set Set UART Mode and set baud rate ACK response data Cannot be set Stop operation received data (86HUART) (Send 86H) Normal response Prepare to enter operation command ACK response data ACK response data & Receive routine Enter operation command data Error Receive error? Received normally RAM transfer? YES (10h) ACK response data received data (10H) ACK response data ACK response data 0x08 Transmission routine (Send x8H: Receive error) SUM? YES (20h) ACK response data Received data (20H) Product information read? Operation command error Erase? YES (30h) ACK response data Received data (30H) YES (40h) ACK response data Received data (40H) ACK response data ACK response data | 0x01 Transmission routine (Send 10H:OK) Transmission routine (Send 20H:OK) Transmission routine (Send 30H: OK) Transmission routine (Send 40H: OK) Transmission routine (Send x1H: Command error) RAM transfer processing SUM processing Product Information Read processing Auto Chip ERASE & UnProtect processing Processed normally? Processed normally Jump to RAM Figure 4.3.6 Overall flowchart for boot program 92FD54AI-52 2006-01-27 TMP92FD54AI 4.4 Programming/Erasing Flash Memory during on-Board Programming The method used for controlling flash memory commands complies with JEDEC standards for standard E2PROMs. For this reason, during RAM transfer operations in User Boot Mode or Single Boot Mode the flash memory is programmed/erased by software commands executed by the CPU. The program for controlling this program/erase operation must be written in advance by the user. Because the flash memory cannot be read while it is being programmed or erased, the program/erase control program must be placed in and executed from the internal RAM or external memory after the device has entered User Boot Mode or after a RAM transfer. 4.4.1 Flash memory With a few exceptions, the functions for programming and erasing the flash memory are based on JEDEC-compliant commands. To program or erase the flash memory, enter a command to the flash memory using the CPU's LD instruction. When a command is entered, the flash memory will automatically be programmed or erased internally. Furthermore, to erase the flash memory, several different methods can be used: all the blocks can be erased together, each block can be erased individually. Table 4.4.1 Flash memory functions Main Functions Auto Program Auto Chip Erase Auto Block Erase Hardware Sequence flags Block Protect Description Automatically writes data and verifies written data in long word units. Automatically erases and verifies all the blocks of the flash memory together. Automatically erases and verifies in units of blocks. Monitoring flags such as a data polling or Toggle Bit flag help to confirm whether the flash memory is being programmed or erased. Block Protect function prevents individual blocks of flash memory from being programmed or erased. As will be described later, in User Boot Mode or during RAM transfer the method of address specification for operation commands differs from that for standard commands for reasons of interfacing with the CPU. Also, unless otherwise stated, the flash memory is written to in units of 32 bits. When writing to flash memory, use 32-bit (long word) data transfer instructions. To enter commands, byte (8-bit) transfer instructions can be used. 92FD54AI-53 2006-01-27 TMP92FD54AI (1) Block configuration Single-Chip F80000H 64 Kbytes Single Boot 010000H 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 56 Kbytes 56 Kbytes 8 Kbytes FFFFFFH 8 Kbytes 08FFFFH Figure 4.4.1 Flash memory block configuration (2) Flash memory interface during on-board programming Figure 4.4.2 is a conceptual diagram of the flash memory's internal interface. Note, however, that this diagram is only a schematic representation of the interface between the CPU and flash memory, and does not represent the actual circuit. Single-Chip Mode: F80000H to FFFFFFH Single-Boot Mode: 010000H to 08FFFFH Operation mode Decoder CE (512 KB) A16 to A2 D31 to D0 WR RD CPU RESET Register AD14 to AD0 DQ31 to DQ0 WE OE RESET RDY/BSY CPU Flash memory A31 to A17 Figure 4.4.2 Flash memory internal interface 92FD54AI-54 2006-01-27 TMP92FD54AI (3) Basic operation Essentially the flash memory on the TMP92FD54AI has the following two modes of operation: * * Mode in which data is read from memory (Read Mode) Mode in which memory data is automatically erased/rewritten (Auto Operation Mode) Auto Operation Mode can be entered from Read Mode by the execution of a command sequence. In Auto Operation Mode no data can be read from the flash memory. 1) Read To read data, set the flash memory to Read Mode. The flash memory is automatically placed in Read Mode immediately after power-on, after the CPU is reset or when auto operation is terminated normally. If auto operation is terminated abnormally, or if you want to return to Read Mode from another mode, either use the Read/Reset command (software reset) or a hardware reset. These are described below. 2) Writing commands The method used for controlling flash memory commands complies with JEDEC standards for standard E2PROMs. To write to the Command Register, execute a command sequence on the flash memory. When the flash memory has latched the input address and data into the Command Register, the program will executes the instruction (see Tables 4.4.3 and 4.4.4). Except for the fourth Read cycle of a Read/Reset and for the fourth Write cycle of an Auto Programonly DQ0 to DQ7 are used to enter commands. Commands can therefore be entered in byte units. If you want to cancel command entry in the middle of a command sequence, enter the Reset command. On accepting the Reset command, the flash memory resets the Command Register and enters Read Mode. Likewise, if an erroneous command sequence is entered, the flash memory resets the Command Register and enters Read Mode. 3) Reset * Read/Reset command (software reset) When auto operation terminates abnormally, the flash memory does not automatically re-enter Read Mode. In this case use the Read/Reset command to return the flash memory to Read Mode. Likewise, to cancel command entry in the middle of a command sequence, use the Read/Reset command to clear the contents of the Command Register. Hardware reset As shown in Figure 4.4.2, the flash memory has a reset input of its own. This input is connected to the CPU's Reset signal. Hence, if the CPU is reset because the device's RESET input pin is pulled Low (VIL) or because the Watchdog timer has overflowed, the current flash memory operation, whether a read operation (write or erase), will stop and the device will either remain in, or re-enter, Read Mode. * 92FD54AI-55 2006-01-27 TMP92FD54AI Also, if auto operation terminates abnormally or if the mode which has been set is cleared by the issuing of a command, the device will re-enter Read Mode due to the CPU being reset. Note that if the device is halted by a hardware reset during auto operation, the flash memory data cannot be rewritten correctly. In this case it is necessary to rewrite the data. For details of the CPU's Reset operation, please refer to Section 4.2.1, Reset operation. After being reset by a designated reset input, the CPU reads reset vector data from the flash memory and starts post-Reset operation. 4) Auto Program Writing to the flash memory involves changing the contents of cells containing 1 to 0. You cannot change 0 to 1. The only way to write 1 to a cell is to erase all the cells. In User Boot Mode or during RAM transfer, data is written to the flash memory in units of 32 bits (long words). Auto Program operation is begun when a program address and program data (in units of long words) are latched in the fourth Bus Write cycle of the Command cycle. Auto programming starts when the flash memory has latched the program data. Since data is written in units of 32 bits, the program address must be incremented by 4. Once program operation has begun, programming and program verification are automatically performed inside the chip. The status of an Auto Program operation can be checked by monitoring the Hardware Sequence flags (see Table 4.4.6). During Auto Program operation, the device will not accept any command sequences input. To stop operation, use a hardware reset. Note that if operation is interrupted, data cannot be written to the flash memory correctly. Data cannot be written to addresses within a protected block. If this is attempted, the device will not execute Auto Program but will enter Read Mode. If Auto Program terminates normally, the device will automatically re-enter Read Mode. If Auto Program terminates in error, the flash memory will be locked into that mode and will not re-enter Read Mode. This status can be confirmed by inspecting the Hardware Sequence flag. To return to Read Mode, it is necessary to reset the flash memory or the device using the Reset command or a hardware reset. In this case, because a write to the protected block address generated an error, it is recommended that the block which contains the bad address not be used or that the device itself not be used. 5) Auto Chip Erase Auto Chip Erase operation starts after the sixth Bus Write cycle of the Command cycle has ended. Once it has started, all flash memory addresses inside the chip are automatically programmed to 0; this is followed by the execution of Erase and Erase Verify. The status of an Auto Chip Erase operation can be checked by monitoring the Hardware Sequence flags (see Table 4.4.5). During an Auto Chip Erase operation, the device cannot accept any command sequences input. To stop operation, use a hardware reset. Note that if operation is interrupted, data cannot be erased correctly and hence the Auto Chip Erase must be re-executed. 92FD54AI-56 2006-01-27 TMP92FD54AI Protected blocks, if any, cannot be erased. If all blocks are protected, the device will not execute Auto Chip Erase but will enter Read Mode. In this case, the deletion operation other block of the following number of the protected block will be excuted. If Auto Chip Erase terminates normally, the device will automatically re-enter Read Mode. If Auto Chip Erase terminates in error, the flash memory will be locked in that mode and will not re-enter Read Mode. The status can be checked by inspecting the Hardware Sequence flag. To return to Read Mode, it is necessary to reset the flash memory or the device using the Reset command or a hardware reset. In this case it will be impossible to detect which block generated the error. Therefore, it is recommended that the bad block be located using the Block Erase function and that henceforth use the bad block not be used. 6) Auto Block Erase An Auto Block Erase starts the Erase Hold time after the sixth Bus Write cycle of the Command cycle has ended. Once it has started, all flash memory addresses in the selected block are automatically programmed to 0; this is followed by the execution of Erase and Erase Verify. If any command sequence other than an Auto Block Erase is entered during the Erase Hold time, the flash memory will be reset and will enter Read Mode. The status of an Auto Block Erase operation can be checked by monitoring the Hardware Sequence flags (see Table 4.4.6). During an Auto Block Erase operation, the device cannot accept any command sequences input. To stop operation, use a hardware reset. Note that in this case, data cannot be erased correctly, and hence the Auto Block Erase must be re-executed. Protected blocks, if any, cannot be erased. If all blocks are protected, the device will not execute Auto Block Erase but will enter Read Mode. If Auto Block Erase terminated in error, the flash memory will be locked in that mode and will not re-enter Read Mode. The status can be checked by inspecting the Hardware Sequence flag. To return to Read Mode, it is necessary to reset the flash memory or the device using the Reset command or a hardware reset. 92FD54AI-57 2006-01-27 TMP92FD54AI 7) Auto Block Protect Auto Block Protect allows individual blocks to be protected from being written or erased. The table below shows the relationship between protection status and the rewrite operation. Table 4.4.2 Block protection status and the Rewrite operation Protection Status and Operation Executed Execute Program on protected block Execute Erase on protected block Execute Chip Erase when all blocks are protected Execute Chip Erase when any blocks are protected Result of executed operation Not programmed and automatically returns to Read Mode Not erased and automatically returns to Read Mode Not erased and automatically returns to Read Mode Only the unprotected blocks are erased. Upon completion, the flash memory automatically returns to Read mode Writing to the protect circuit is initiated by the address of the block to be protected in the sixth Bus Write cycle of the command sequence, and set data to "70H". (see Figure 4.4.8) During automatic operation no other command sequence input can be accepted. To stop operation use a hardware reset. When it erases Auto Block Protect, use Auto Chip Erase & Unprotect command. (see Table 4.4.3) In this case it erases all Auto Block Protect and all blocks of the flash memory. 8) Verify Block Protect Verify Block Protect is used to check whether or not blocks are protected. Enter the address of the block you want to check in the fourth Bus Read cycle of the command sequence. At this time, specify an address where A3 = A6 = 0, A4 = 1, and read the selected block in units of long words. If the block is protected, the data returned will be 00000001H. Conversely, if the block is unprotected, the data returned will be 00000000H. To continue verifying the protection of other blocks, it is only necessary to repeating the fourth Bus Read cycle so as to read out data from each block. Change the block address as desired and read the data out in long words. To return to Flash Memory Read or any other command input after the Verify Block Protect has been completed, it is necessary to issue a Read/Reset command or a hardware reset. 9) Hardware Sequence flags (see Table 4.4.6) The status of automatic execution of operations on flash memory can be checked by inspecting the Hardware Sequence flags. During automatic operation data can be read out with the same timing as that of Read Mode. The flash memory automatically returns to Read Mode after automatic operation has finished. During automatic execution it is possible to monitor the operating status by inspecting the Hardware Sequence flags. After automatic operation has finished, the operating status can be confirmed by checking the read data to see that it matches the cell data. To inspect the Hardware Sequence flags during an Auto Program operation, specify the same address as the one which has been set by the rewrite routine (in which A0 = A1 = 0) at the same time as reading out the flag. Also, to inspect the Hardware Sequence flags during an Auto Erase operation, specify an address in which A0 = A1 = 0 at the same time as reading out the flag. 92FD54AI-58 2006-01-27 TMP92FD54AI * DQ7 (Data Polling) The Data Polling function allows confirmation of the status of automatic operations on flash memory. Data polling output begins after the last Bus Write cycle of an automatic operation command sequence has ended. During an Auto Program operation the data written to DQ7 is output after being inverted. After an Auto Program operation, the cell data for DQ7 itself is output so that the operation status can be identified by reading DQ7. During an Auto Erase operation the data 0 is output on DQ7; after an Auto Erase operation the data 1 (the cell data) is output on DQ7. If an automatic operation resulted in an error, DQ7 will continue to output the data it held during the automatic operation. Therefore, this data can be used in combination with the value on DQ5 (the internal timer-out) to determine whether failure has occurred (see Figure 4.4.6). Since the flash memory releases the address latch on completion of operation, to read out data it is necessary to specify either the address to which data has been written or the address of any unprotected erased block. * DQ6 (Toggle bit) The Toggle bit function, same as the data polling function, allows confirmation of the status of automatic operations on flash memory. The Toggle output begins after the last Bus Write cycle of an automatic operation command sequence has ended on DQ6. Every read cycle, output reciprocally 0 and 1. If an automatic operation resulted in an error, DQ6 will continue to output the data it held during the automatic operation. Therefore, this data can be used in combination with the value on DQ5 (the internal timer-out) to determine whether failure has occurred (see Figure 4.4.6). DQ5 (internal time-out) Normally when automatic operation is in progress, the flash memory outputs 0 on DQ5. If the automatic operation exceeds the flash memory's internal time-out period, the DQ5 output will change state to 1. This indicates that automatic operation did not terminate normally and suggests that the flash memory may be faulty. Furthermore, since the flash memory can have its cells changed from data 1 to data 0 in Program Mode, but cannot have its cells changed from data 0 to data 1, if an attempt is made to write a data 1 to a data 0 cell, the device will not be able to write data correctly within the predetermined time. As a result, the device will output a 1 on DQ5, just as if the flash memory were found to be faulty. In this case the value on DQ5 is not indicating that the flash memory is faulty, but that an attempt to perform an invalid operation was made. If automatic operation did not terminate normally, the flash memory will be locked and will not re-enter Read Mode. Therefore, reset the flash memory using the Reset command. * * DQ3 (Block Erase timer) Auto Block Erase starts the Block Erase Hold time after the sixth Bus Write cycle of the Command cycle has ended. The flash memory outputs a 0 on DQ3 during the Block Erase Hold time and outputs a 1 when it starts an Erase operation. 92FD54AI-59 2006-01-27 TMP92FD54AI 10) Flash Status Register This is an 8-bit register which serves purposes of a flash memory status monitor. 7 R/W 0 Set to 0. Bit symbol Read/Write After reset 6 R/W 0 Set to 0. Flash status register 5 4 R/W R/W 0 0 Set to 0. Set to 0. 3 - 2 R/BSY R 1 Ready /Busy flag 1 - 0 - FLSR (16EH) Function 0:Busy (auto operation in progress) 1:Ready (auto operation finished) Figure 4.4.3(1) Flash Status Register Bit 2: Ready/Busy Flag bit The device has a RDY/BSY output which enables the status of automatic operation to be recognized by the host in Programmer Mode. This bit is used to monitor the RDY/BSY output from the CPU. When automatic operation is being performed on the flash memory, this bit outputs a 0, indicating that the flash memory is busy. When automatic operation has finished, it will output 1 and the flash memory will be ready to accept the next command. If automatic operation results in error, this bit will continue to output 0. The bit is reset to 1 by a hardware reset. The bit outputs 0 starting from completion of the last Bus Write cycle of the automatic operation command sequence. For an Auto Block Erase, however, it starts outputting 0 the Erase Hold time after the said cycle has ended. If this bit = 0, no command sequence input can be accepted. 11) FLASH Security Write Enable Register This is an 8-bit register which allows to enable Auto Chip Erase & Unprotect command. FLASH Security Write Enable Resister Bit symbol Read/Write After reset Function 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 FSWE (16BH) C9H:Auto Chip Erase & Unprotect command Enable code Others: Auto Chip Erase & Unprotect command Disable code Figure 4.4.3(2) FLASH Security Write Enable Register Pleas write it in the FSWE register when you execute the program with RAM. 92FD54AI-60 2006-01-27 TMP92FD54AI (4) Command sequence list Table 4.4.3 Flash memory access by internal CPU Command Sequence Read/Reset Read/Reset Auto Program Auto Chip Erase Auto Block Erase Auto Block Protect Verify Block Protect Auto Chip Erase & Unprotect *1 Number of Bus Cycles 1st Bus Write Cycle Addr. Data F0H AAH AAH AAH AAH AAH AAH AAH 2nd Bus Write Cycle Addr. Data x5554H x5554H x5554H x5554H x5554H x5554H x5554H 55H 55H 55H 55H 55H 55H 55H 3rd Bus Write Cycle Addr. Data xAAA8H xAAA8H xAAA8H xAAA8H xAAA8H xAAA8H xAAA8H F0H A0H 80H 80H 9AH 90H 80H 4th Bus Read/Write Cycle Addr. Data RA RD PA PD xAAA8H AAH xAAA8H AAH xAAA8H AAH BPA BD xAAA8H AAH 5th Bus Write Cycle Addr. Data 6th Bus Write Cycle Addr. Data 1 xXXX0H 3 xAAA8H 4 xAAA8H 6 xAAA8H 6 xAAA8H 6 xAAA8H 4 xAAA8H 6 xAAA8H x5554H x5554H x5554H x5554H 55H 55H 55H 55H xAAA8H BA BA xAAA8H 10H 30H 70H 10H Note: There must be an interval of at least two instructions between each Bus Cycle. *1 When this command is operated, be sure to set FSWE. The addresses to be accessed from the CPU are shown below. Table 4.4.4 Relationship between addresses Command Address Addr. 0000H AAA8H 5554H CPU Addresses: A23 to A0 A23 A16 A15 A14 A13 A12 A11 A10 0 0 0 0 0 0 Flash memory 1 0 1 0 1 0 address 0 1 0 1 0 1 area A9 0 1 0 A8 0 0 1 A7 0 1 0 A6 0 0 1 A5 0 1 0 A4 0 0 1 A3 0 1 0 A2 0 0 1 A1 0 0 0 A0 0 0 0 (5) Additional explanation * F0H, AAH, 55H, A0H, 80H, 10H, 30H: Command data. Write data in units of bytes. * RA: Read address RD: Read data output * PA: Program address PD: Program data input * BA: Block address (BA0~BA6) * BPA: Verify Block Protect address Write data to addresses which are divisible by 4 in units of long word Please refer to Table 4.4., Block Erase addresses. Please refer to part 8), entitled Verify Block Protect, on page 58 of Section 3.4.1 (3), Basic operation. If the block is protected, the data 0x0000_0001 will be returned; if it is not protected, the data 0x0000_0000 will be returned. * BD: Block Protect data 92FD54AI-61 2006-01-27 TMP92FD54AI Table 4.4.5 Block Erase addresses Block BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA9 Address Area User Boot Mode Single Boot Mode F80000H to F8FFFFH F90000H to F9FFFFH FA0000H to FAFFFFH FB0000H to FBFFFFH FC0000H to FCFFFFH FD0000H to FDFFFFH FE0000H to FEDFFFH FEE000H to FFBFFFH FFC000H to FFDFFFH FFE000H to FFFFFFH 010000H to 01FFFFH 020000H to 02FFFFH 030000H to 03FFFFH 040000H to 04FFFFH 050000H to 05FFFFH 060000H to 06FFFFH 070000H to 07DFFFH 07E000H to 08BFFFH 08C000H to 08DFFFH 08E000H to 08FFFFH Size 64Kbite 64Kbite 64Kbite 64Kbite 64Kbite 64Kbite 56Kbite 56Kbite 8Kbite 8Kbite Enter an address within the address area of the block to be selected. This should be an address for which A0 = A1 = 0. Example: To select BA0 in User Boot Mode, enter any address in the area F80000H to F8FFFFH. Table 4.4.6 Hardware Sequence flags Status Auto Program Automatic operation Auto Erase (during Erase Hold time) in progress Auto Protect Program Auto Chip Erase & Unprotect Auto Program Time-out (automatic Auto Erase operation failed) Auto Protect Program Auto Chip Erase & Unprotect READ Complete normally D7 (DQ7) D6 (DQ6) D5 (DQ5) D3 (DQ3) /D7 0 * * /D7 0 * * Cell data Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Cell data 0 0 0 0 1 1 1 1 Cell data 0 1 0 1 0 1 0 1 Cell data Note: The settings for D31 to D8, D4 and D2 to D0 are "Don't care". 92FD54AI-62 2006-01-27 TMP92FD54AI (6) Flowchart Start Auto Program command sequence (See the flow shown below.) Data polling, Toggle bit (read out in units of long words) Address = Address + 4 (in units of long words) No Last address? YES Auto Program finished Auto Program command sequence (address/command) xAAA8H/AAH X5554H/55H xAAA8H/A0H Program address (A1, A0 = 0)/ Program data (in units of long words) Figure 4.4.4 Auto Program 92FD54AI-63 2006-01-27 TMP92FD54AI Start Auto Erase command sequence (see the flow shown below) Data polling, Toggle bit (read out in units of long words) Auto Erase finished Auto Chip Erase command sequence (address/command) xAAA8H/AAH Auto Block Erase command sequence (address/command) xAAA8H/AAH x5554H/55H x5554H/55H xAAA8H/80H xAAA8H/80H xAAA8H/AAH xAAA8H/AAH x5554H/55H x5554H/55H xAAA8H/10H Block address / 30H Figure 4.4.5 Auto Erase 92FD54AI-64 2006-01-27 TMP92FD54AI Start Read long word Addr. = VA DQ7 = Data ? No No DQ5 = 1 ? Yes Read long word Addr. = VA Yes DQ7 = Data ? No Terminates abnormally Yes Terminates normally Figure 4.4.6 DQ7 data polling Start Read long word Addr. = VA DQ6 = Data ? No No DQ5 = 1 ? Yes Read long word Addr. = VA Yes DQ6 = Data ? VA: The address of writing data (auto program) The address of any flash memory address.(auto chip erase) The address of selected block address (auto block erase) No Terminates abnormally Yes Terminates normally Figure 4.4.7 DQ6 toggle bit 92FD54AI-65 2006-01-27 TMP92FD54AI Start xAAA8H/AAH x5554H/55H xAAA8H/9AH xAAA8H/AAH x5554H/55H Block address/70H Block protect finished Figure 4.4.8 Auto Block Protect 92FD54AI-66 2006-01-27 TMP92FD54AI Start xAAA8H/AAH x5554H/55H xAAA8H/80H xAAA8H/AAH x5554H/55H xAAA8H/10H Figure 4.4.10 Auto Chip Erase & Unprotect 92FD54AI-67 2006-01-27 TMP92FD54AI 5. Electrical Characteristics 5.1 Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Output Current(total) Output Current(total) Power Dissipation(Ta=85degree C) Soldering Temperature(10s) Storage Temperature Operation Temperature Operation Temperature (Flash Program / Erase) The number of write erase cycles Symbol VCC5 VIN IOL IOH PD TSOLDER TSTG TOPR NEW Rating -0.5 to 6.0 -0.5 to VCC5+0.5 100 -100 600 260 -65 to 150 -40 to 85 0 to 70 100 Unit V V mA mA mW degree C degree C degree C Cycle Note: The absolute maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products that include this device, ensure that no absolute maximum rating value will ever be exceeded. 92FD54AI-68 2006-01-27 TMP92FD54AI 5.2 DC Electrical Characteristics Vcc5 =4.5V to 5.25V / fc = 16 to 20MHz / Ta = -40 to 85 degree C Parameter Supply Voltage Input Low Voltage Symbol VCC5 VIL0 Condition Min 4.5 -0.3 Max 5.25 0.8 Unit V V P00 to P07(D0 to 7) PG0 to PG7 PL0 to PL3 Input Low Voltage P00 to P07(PORT) P40 to P47 Input Low Voltage VIL1 -0.3 0.3*VCC5 V INT0 NMI RESET P70, P71, P73 to P75 VIL2 PC0 to PC5 PD0 to PD7 PF0 to PF7 PM0 to PM4 P72, PN0 to PN6 VIL6 Input Low Voltage -0.3 0.25*VCC5 V -0.3 -0.3 0.3*VCC5 0.3 0.2*VCC3 0.2*VCC3 V V V V AM0 to AM1 TEST0 to TEST1 Input Low Voltage VIL3 VIL4 VIL5 VIH0 X1, XT1 (Crystal) Input Low Voltage * Vcc3 = 3.3V * Vcc3 = 3.3V -0.3 -0.3 XT1 (CR) Input High Voltage P00 to P07(D0 to 7) PG0 to PG7 PL0 to PL3 Input High Voltage 2.2 VCC5+0.3 V P00 to P07 P40 to P47 Input High Voltage VIH1 0.7*VCC5 VCC5+0.3 V INT0 NMI RESET P70, P71, P73 to P75 VIH2 PC0 to PC5 PD0 to PD7 PF0 to PF7 PM0 to PM4 P72, PN0 to PN6 VIH6 Input High Voltage 0.75*VCC5 VCC5+0.3 V 0.7*VCC5 VCC5-0.3 VCC5+0.3 VCC5+0.3 VCC3+0.3 VCC3+0.3 V V V V AM0 to AM1 TEST0 to TEST1 Input High Voltage VIH3 VIH4 VIH5 X1, XT1 (Crystal) Input High Voltage * Vcc3 = 3.3V * Vcc3 = 3.3V 0.8*VCC3 0.7*VCC3 XT1 (CR) 92FD54AI-69 2006-01-27 TMP92FD54AI Parameter Output Low Voltage Symbol VOL VOH0 VOH1 VOH2 VOHn ILI ILO ICC5 ICC5IDLE2 ICC5IDLE1 Condition IOL = 3.0mA IOH = -400uA IOH = -100uA IOH = -20uA IOH = -200uA, PF6(TX) pin 0.0 Vin VCC5 0.2 Vin VCC5-0.2 VCC5=5.25V , X1=10MHz(Internal 20MHz) IDLE2 Mode IDLE1 Mode IDLE3 Mode STOP Mode Min 2.4 0.75*VCC5 0.9*VCC5 0.82*VCC5 0.02(typ.) 0.05(typ.) 80(typ) Max 0.4 Unit V Output High Voltage V Input Leakage Current Output Leakage Current Operating Current +/- 5 +/- 10 100 90 uA uA mA (Single Chip)* VCC5=5.25V, X1=10MHz(Internal 20MHz) mA VCC5=5.25V, X1=10MHz(Internal 20MHz) 30 220 140 200 120 3.0 5.25 uA uA V K ohm Operating Current (Stand-by) ICC5IDLE3 ICC5STOP VCC5=5.25V, Ta = -40 to 85 degree C VCC5=5.25V, Ta = -10 to 55 degree C VCC5=5.25V, Ta = -40 to 85 degree C VCC5=5.25V, Ta = -10 to 55 degree C VCC3 < VCC5 , VIH1 220 0.4 1.0(typ.) V 92FD54AI-70 2006-01-27 TMP92FD54AI Flash Single-boot Mode Parameter Symbol Mean operating current IDDO1 (during reading) Mean operating current IDDO2 (during programming) Mean operating current IDDO3 (during erasing) Standby current IDDS Vcc5 =4.5V to 5.25V / fc = 16 to 20MHz / Ta = -40 to 85 degree C ( Ta=0 to 70 degree C during programming or erasing of flash memory) Condition Min Max Unit 80 fc = 20 MHz VCC5=5.25V, Ta = -40 to 85 degree C VCC5=5.25V, Ta = -10 to 55 degree C 100 100 110 200 120 mA mA mA uA Note: Precautions when programming/erasing flash memory 1) In On-Board Programming Mode (Single-Boot Mode or User Boot Mode), inhibit all interrupts including NMI to allow the highest priority for program/erase operations. 2) To rewrite data in already programmed addresses, execute an Auto Erase before executing Auto Program. 92FD54AI-71 2006-01-27 TMP92FD54AI 5.3 AC Characteristics Read cycle No. 1 2 3 4 5-1 5-2 6-1 6-2 7-1 7-2 8 9 10 11 12 13 14 15 Parameter OSC period (X1/X2) System Clock period (=T) CLK Low Width CLK High Width A0 to A23 Valid D0 to D7 Input 0WAIT A0 to A23 Valid D0 to D7 Input 1WAIT RD Fall D0 to D7 Input 0WAIT RD Fall D0 to D7 Input 1WAIT RD Low Width 0WAIT RD Low Width 1WAIT A0 to A23 Valid RD Fall RD Fall CLK Fall A0 to A23 Valid D0 to D7 Hold RD Rise D0 to D7 Hold A0 to A23 Valid PORT Input A0 to A23 Valid PORT Hold WAIT Set-up Time WAIT Hold Time Symbol tOSC tCYC tCL tCH tAD tAD3 tRD tRD3 tRR tRR3 tAR tRK tHA tHR tAPR tAPH tTK tKT Min 100 50 0.5xT-15 0.5xT-15 VCC5=4.5 to 5.25V5%, TA=--40 to 85 degree C Max 20MHz 16MHz Unit 125 100 125 ns 62.5 50 62.5 ns 10 16 ns 10 16 ns 2.0xT-50 50 75 ns 3.0xT-50 100 138 ns 1.5xT-45 30 49 ns 2.5xT-45 80 111 ns 55 74 ns 105 136 ns 5 11 ns 5 11 ns 0 0 ns 0 0 ns 2.0xT-120 -20 5 ns 100 125 ns 15 15 ns 5 5 ns 1.5xT-20 2.5xT-20 0.5xT-20 0.5xT-20 0 0 2.0xT 15 5 Write cycle No. 1 2 3 4 5-1 5-2 6-1 6-2 7 8 9 10 11 12 13 14 Parameter OSC period (X1/X2) System Clock period (=T) CLK Low Width CLK High Width D0 to D7 Valid WR Rise 0WAIT D0 to D7 Valid WR Rise 1WAIT WR Low Width 0WAIT WR Low Width 1WAIT A0 to A23 Valid WR Fall WR Fall CLK Fall WR Fall A0 to A23 Hold WR Fall D0 to D7 Hold A0 to A23 Valid PORT Output WAIT Set-up Time WAIT Hold Time RD Rise D0 to D7 Output Symbol tOSC tCYC tCL tCH tDW tDW3 tWW tWW3 tAW tWK tWA tWD tAPW tTK tKT tRDO Min 100 50 0.5xT-15 0.5xT-15 1.25xT-35 2.25xT-35 1.25xT-30 2.25xT-30 0.5xT-20 0.5xT-20 0.25xT-5 0.25xT-5 15 5 1.25xT-35 Max 125 62.5 VCC5=5.0V5%, TA=--40 to 85 degree C 20MHz 100 50 10 10 28 78 33 83 5 5 8 8 170 15 5 20 16MHz 125 62.5 16 16 43 106 48 111 11 11 11 11 195 15 5 26 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2.0xT+70 AC Condition Output : Input : D0 to D7, A0 to A7, A8 to A15, A16 to A23, RD, WR High 2.0V, Low 0.8V, CL=50pF Others High 2.0V, Low 0.8V, CL=50pF D0 to D7 High 2.4V, Low 0.45V, CL=50pF Others High 0.8xVCC5, Low 0.2xVCC5 92FD54AI-72 2006-01-27 TMP92FD54AI (1) Read cycle (0 wait) tOSC X1 tCYC tCL CLK (fc) tCH tTK WAIT tKT A0 to A23 tAD CS tHA tAR RD tRK tHR tRR tRD D0 to D7 Data Input tAPH tAPR Port input Port Input Note : The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. 92FD54AI-73 2006-01-27 TMP92FD54AI (2) Write cycle (0 wait) tOSC X1 tCYC tCL CLK (fc) tCH tTK WAIT tKT A0 to A23 CS tAW WR tWK tWA tWW tDW D0 to D7 tWD tRDO RD Data Output tAPW Port output Note : The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. 92FD54AI-74 2006-01-27 TMP92FD54AI (3) Read cycle (1 wait) CLK (fc) WAIT A0 to A23 tAD3 CS RD tRD3 D0 to D7 tRR3 Data Input (4) Write cycle (1 wait) CLK (fc) WAIT A0 to A23 CS WR tDW3 D0 to D7 RD tWW3 Data Output tRDO 92FD54AI-75 2006-01-27 TMP92FD54AI 5.4 AD Conversion Characteristics Symbol VREFH VREFL AVCC AVSS AVIN IREF Parameter Analog reference voltage() Analog reference voltage() AD Converter Power Supply Voltage AD Converter Ground Analog Input Voltage Analog Current for analog reference voltage Total error (excluding quantize error) Min VCC5-0.2 VSS5 VCC5-0.2 VSS5 VREFL Typ VCC5 VSS5 VCC5 VSS5 0.8 0.02 MAX VCC5 VSS5 VCC5 VSS5 VREFH 1.2 5 3.0 Unit V mA uA LSB ET Note) "LSB" is the UNIT which means the resolution of AD CONVERTER. (+/- 3 LSB = 3 * VCC/1024 = +/-15mV) 5.5 Event Counter (TI0, TI4, TI8, TI9, TIA, TIB) Parameter Symbol Clock Cycle Clock Low Width Clock High Width tVCK tVCKL tVCKH Variable Min Max 8T+100 4T+40 4T+40 20MHz Min Max 500 240 240 16MHz Min Max 600 290 290 Unit ns ns ns 5.6 Serial Channel Timing (1) SCLK Input mode (I/O Interface mode) Parameter SCLK Cycle Output Data SCLK Rise SCLK Rise Output Data Hold SCLK Rise Input Data Hold SCLK Rise Input Data Valid Symbol Variable Min 16T tSCY/2-4T -110 tSCY/2+2T 3T+10 tSCY Max tSCY tOSS tOHS tHSR tSRD 20MHz Min Max 0.8 90 500 160 800 16MHz Min Max 1.0 140 625 197.5 1000 Unit us ns (2) SCLK Output mode (I/O Interface mode) Parameter SCLK Cycle (programmable) Output Data SCLK Rise SCLK Rise Output Data Hold SCLK Rise Input Data Hold SCLK Rise Input Data Valid Symbol Variable Min 16T tSCY/2-40 tSCY/2-40 0 tSCY/2-T -180 Max 8192T tSCY tOSS tOHS tHSR tSRD 20MHz Min Max 0.8 409.6 360 360 0 570 16MHz Min Max 1.0 512 460 460 0 757.5 Unit us ns 92FD54AI-76 2006-01-27 TMP92FD54AI tSCY SCL tOSS OUTPUT DATA TxD INPUT DATA RxD 0 tOHS 1 tSRD VALID tHSR VALID (3) SCLK Input mode (UART mode) (Preliminary) Parameter SCLK Cycle SCLK Low level Pulse width SCLK High level Pulse width Symbol TSCY TSCYL TSCYH Variable Min Max 4T + 20 2T + 5 2T + 5 20MHz Min Max 220 105 105 16MHz Min Max 270 130 130 Unit ns 5.7 Interrupt Operation Parameter NMI,INT0 Low Width NMI,INT0 High Width WUINT0 to WUINT7, INT1 to INT7 Low Width WUINT0 to WUINT7, INT1 to INT7 High Width Symbol Variable Min 4T 4T 8T+100 8T+100 Max TINTAL TINTAH TINTBL TINTBH 20MHz Min Max 200 200 500 500 16MHz Min Max 250 250 600 600 Unit ns 92FD54AI-77 2006-01-27 TMP92FD54AI 5.8 Serial bus interface I2CBUS-AC-SPEC TABLE 5.8 Serial bus interface No PARAMETER SYMBOL UNIT (fc=) KH MIN MAX 0 650 1300 600 400 100KHz MIN MAX 0 4500 4700 4000 100 - (fc=System clock) Existing rate MIN MAX 0 1 SCL clock frequency KHz ns ns ns ns ns ns fc/(2 +8) - n Hold time (repeated) START condition. 2 After this period, the first clock pulse is generated. HDSTA 3 LOW period of the SCL clock 4 HIGH period of the SCL clock 5 Set-up time for a repeated START condition LOW HIGH SUSTA 2 /fc 2 /fc (2 +8)/fc n-1 n-1 n-1 by software 0 100 950 900 300 (receive) 300 400 0.2VDD5 0.2VDD5 0 50 by software 0 250 4200 3450 - by software 0 Data hold time: 6 for CBUS compatible masters for I2C-bus devices HDDAT 7 Data set-up time Data set-up time ' (The case in the first bit after transfer ) 8 Rise time of both SDA and ACL signals (*1) SUDAT 6/fc - (2 -6)/fc n-1 SU1stDAT r SUSTO BUF Cb VnL VnH tsp ns ns ns ns pF v v ns n-1 (2 -12)/fc 1000 (receive) 9 Fall time of both SDA and ACL signals 10 Set-up time for STOP condition Bus free time between a STOP and START 11 condition 12 Capacitive load for each cus line Noise margin at the LOW level for each connected 13 device (including hysteresis) Noise margin at the HIGH level for each connected 14 device (including hysteresis) Pulse width of spikes which must be 15 suppressed by the input filter Note 1 All values referred to VIHmin and VILmax levels. 300 400 n-1 - (2 +12)/fc 400 by software by software by software 0.2VDD5 0.2VDD5 n/a - 0.2VDD5 0.2VDD5 n/a - n/a n/a S SDA SU:1stDAT SU:DAT HIGH Sr P S f SCL LOW HD:STA SP r BUF HD:STA S : Start P :Stop r HD:DAT f SU:STA SU:STO Sr : ReStart *1) I2BUS CLK AC SPEC : Tr (Transmitter selection ) Vih SCLK T-Low SCK(0001 - 0110) SCK(1111) :100KHz SCK(1000) :400KHz 2*(n-1)/fc 100/fc 32/fc Tr T-High (2*(n-1)+8)/fc 100/fc 18/fc SCK(0001 - 0110) SCK(1111) :100KHz SCK(1000) :400KHz Tr T-R T-R T-R 0 to 2/fc 0 0 0 4/fc to 6/fc 2/fc to 4/fc 4/fc 4/fc 2/fc 4/fc 6/fc to 8/fc 8/fc to 10/fc 8/fc 8/fc 8/fc 6/fc .... .... .... .... T-period = T-Low + T-R + T-High Example: in the case of fc=20MHz, SCK3,2,1,0=(0001), Tr=200ns 1) Tr=200ns so T-R=4/fc 2) T-period = 2*(n-1)/fc + 4/fc + (2*(n-1)+8)/fc =76/fc =3.8us 92FD54AI-78 2006-01-27 TMP92FD54AI 5.9 Serial Expansion Interface Symbol t SECLK t LEAD t LAG t SCKH t SCKL t SU tH tV t HO Parameter SECLK Cycle SS fall SECLK SECLK SS rise SECLK High Pulse Width SECLK Low Pulse Width Input Data Set-up Input Data Hold Output Data Valid Output Data Hold Variable Min Max 5T 40T 4T 4T t SECLK /2-9 t SECLK /2-9 t SECLK /4-10 t SECLK /4 t SECLK /4 0 20MHz Min 250 200 200 116 116 52 62 0 Max 2000 Unit ns ns ns ns ns ns ns ns ns 62 a) SEI Master (CPHA=0) SS tSECLK SECLK tSCKL SECLK tSU MISO MOSI MSB Input MSB Output bit6 to 1 bit6 to 1 tH LSB Input tV LSB Output tHO tSCKH b) SEI Master (CPHA=1) SS tSECLK SECLK SECLK tSU MISO MOSI MSB Input MSB Output bit 6 to 1 bit 6 to 1 tH LSB Input tV LSB Output tHO 92FD54AI-79 2006-01-27 TMP92FD54AI c) SEI Slave (CPHA=0) SS tLEAD SECLK SECLK tHO MISO MOSI MSB Output tSU MSB Input tV bit 6 to 1 bit 6 to 1 LSB Output tH LSB Input tSCKH tSCKL tLAG d) SEI Slave (CPHA=1) SS tLEAD SECLK tSCKL SECLK tV MISO MOSI MSB Output tSU MSB Input bit 6 to 1 bit 6 to 1 tHO LSB Output tH LSB Input tSCKH tLAG 5.10 Controller Area Network (CAN) Symbol tcclk tp Parameter CAN Clock period Tx edge Rx Input Variable Min 2T Max 2tcclk-20 Min 100 20MHz Max 180 Unit ns ns Tx Rx tp tp 92FD54AI-80 2006-01-27 TMP92FD54AI 5.11 Voltage regulator Voltage Regurator Parameter Output Voltage Output Current Quiescent Current Symbol REGOUT Iro Iq Iq1 Iop Is Vcc5 =4.5V to 5.25V / fc = 16 to 20MHz / Ta = -40 to 85 degree C Condition Vin-REGOUT=1.0V Iro10 uA 10 uAIro100mA (Ta=25) Iro=150mA REGEN=0 (Regulator Only) Min. 3.0 0 30 15 6 Typ. 50 250 8 0.1 Max. 3.6 150 100 800 10 0.2 Unit. V mA A A mA A Standby Current 0.5[Ohm] ESR5.0[Ohm] Parameter Stabilization capactor Bypass capactor Input capactor Equivalent Series Resistor Symbol Cs Cb Cin (Note) ESR Condition Cb=10uF, ESR=4.7 Cs=10uF, ESR=4.7 (Cs>=Cb) Cs=10uF, ESR=4.7 Cs=10uF Cb=0.1uF Min. 0.1 0.1 4.7 0.5 Typ. Max. 10 10 22 5 Unit. F F F 0.5[Ohm] ESR50[Ohm] Parameter Stabilization capactor Bypass capactor Input capactor Equivalent Series Resistor Symbol Cs Cb Cin (Note) ESR Condition Cb=0.6uF, ESR=47 Cs=10uF, ESR=47 (Cs>=Cb) Cs=10uF, ESR=47 Cs=10uF Cb=0.6uF Min. 0.1 0.6 4.7 0.5 Typ. Max. 10 10 22 50 Unit. F F F 0.5[Ohm] ESR100[Ohm] Parameter Stabilization capactor Bypass capactor Input capactor Symbol Cs Cb Cin (Note) ESR Condition Cb=1.0uF, ESR=100 Cs=10uF, ESR=100 (Cs>=Cb) Cs=10uF, ESR=100 Min. 0.1 1.0 4.7 0.5 Typ. Max. 10 10 22 100 Unit. F F F Equivalent Cs=10uF Cb=1.0uF Series Resistor Note: Recommend Tantalum Capacitor. DVCC3 Cb TMP92FD54AI DVCC5 Cin REGOUT REGEN Cs ESR DVSS OPEN 92FD54AI-81 2006-01-27 TMP92FD54AI 6. 6.1 Points to Note and Restrictions Notation (1) The notation for built-in I/O registers is as follows register symbol Examples of read-modify-write instructions on the TLCS-900/H1 Exchange instruction EX (mem), R Arithmetic operations ADD (mem), R/# SUB (mem), R/# INC #3, (mem) Logic operations AND (mem), R/# XOR (mem), R/# Bit manipulation operations STCF #3/A, (mem) SET #3, (mem) TSET #3, (mem) Rotate and shift operations RLC (mem) RL (mem) SLA (mem) SLL (mem) RLD (mem) . RRC RR SRA SRL (mem) (mem) (mem) (mem) RES #3, (mem) CHG #3, (mem) OR (mem), R/# ADC (mem), R/# SBC (mem), R/# DEC #3, (mem) RRD (mem) 92FD54AI-82 2006-01-27 TMP92FD54AI 6.2 Points to Note (1) Watchdog timer The watchdog timer starts operation immediately after a reset is released. When the watchdog timer is not to be used, disable it. (2) The stable time of the internal clock When releasing the external reset using "built-in clock doubler" until the internal reset is released, the requiring time to stabilize the circuit is automatically set. See section 3.1.2 "Reset Operation" for details. Also when releasing standby mode in STOP mode using an interrupt until the internal circuit starts the operation, the stable time of the oscillator is automatically input. See section 3.4 "Standby Function (3) STOP mode" for details. (3) Undefined bit in the built-in I/O register When reading the undefined bit in the built-in I/O register, the undefined value is output. Thus, when creating program, it should not be depending on this bit condition. (4) Reserved address areas The 16 bytes area (FFFFF0H to FFFFFFH) cannot be used for it is reserved as internal area. If using emulator, optional 64 Kbytes of 16M bytes area are used for control emulator. Therefore, if using emulator, its area cannot be used. (5) POP SR instruction Execute the POP SR instruction during DI condition. 92FD54AI-83 2006-01-27 TMP92FD54AI 7. Package Package DimensionsP-LQFP100-1414-0.50C 16.00.2 14.00.2 75 1.0TYP 76 50 51 Unit : mm 100 26 1 25 0.2 0.1 1.0TYP 0.5 1.40.2 14.00.2 0.08 M 16.00.2 1.85MAX 15.00.2 0.125 -0.05 +0.1 0~10 0.50.2 92FD54AI-84 0.1 -0.1 +0.15 0.08 2006-01-27 |
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